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How to readback a register contents from FPGA to PC via JTAG or UART?

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msdarvishi

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Hello,

I am using ISE 14.7 targetting a Virtex-5 FPGA. I defined some signals as registers to stores some values in. I would like to know how is it possible to readback the content of those signals (registers) from FPGA back to PC?? I am thinking to UART via Hyperterminal or JTAG but I do not know how to configure it? Can anybody help me by that? What is the command, architecture, etx that I have to configure to do that?

Kind helps are in advance appreciated.
Regards,
 

Hi,

Just build a UART transmitter.

It should have
* a clock input to generate baud rate
* a data input. Connect it with the register you want to read
* a trigger input to start transmission. Generate a pulse every time you want to read/transmit data.

You hould find a UART ip.
Show us the code.

Klaus
 

Besides what Klaus states you'll also have to use a protocol that transmits the address prior to the data transfer either sending data (write) or receiving data (read).
 

There are a few main methods to solve this problem.

The first and easiest is to generate a periodic broadcast of state. This works best when only a few registers exist and updates are infrequent. In this case, you have a uart controller of some sort. Then you have a state machine that generates some form of strobe/capture signal and then selects between the registers. The strobe makes a copy of any transmitted register that does not change until the next strobe. There are variations on this, for example placing the large mux before the capture register instead of having several capture registers and a large mux.

The state machine can send out a fixed format of some form or another. eg, a short header followed by data followed by some checksum (if desired). This method works for a uart, where either side can transmit freely.


For jtag (and also uart), you can also have a protocol where some value is transmitted from the PC and results in a value being returned. This works well when interaction is required -- when you want reads and writes and anything more advanced (block read/write, masked read/write, etc...) This requires knowing how to read from the uart/jtag (or ethernet/i2c/spi/etc...) core you use.
 

If it is only for debugging purposes, you can use chipscope with the JTAG port. It is the easy way to do.
 

While I am not sure about Xilinx, I know that for Altera they have something called "SignalTap II". Basically, we specify signals in specific parts of the design that we want to probe. When the design is synthesized these points are routed to registers (or memory blocks) within the device. These registers are only used for debug purpose and, by using JTAG and specified trigger setting, we can use the SignalTapII just like a logic analyzer. The extra debug logic continuosly stores data into itself. When the trigger condition occurs, this data is transmitted to the PC via JTAG albeit at a much slower rate than the design operates.

I am sure that Xilinx have something silimar. Using SignalTap II Lo and behold one can actually see INSIDE the design! Search for the equivalent tool for Xilinx. I am sure it exists. Adding this automatically generated debug logic may cause less than optimal fitting for our actual design as the debug logic shall also use the logic resources. In some cases, if we have very limited resources left in the programmable logic part of the FPGA, the debug logic may not fit. The size of the debug logic depends on the arbitrarily chosen memory depth and how many signals we want to "probe".
 

ads-ee said:
Besides what Klaus states you'll also have to use a protocol that transmits the address prior to the data transfer either sending data (write) or receiving data (read).
Click to expand...


Thanks @ads-ee for your kind reply. Indeed I have a protocol for UART with 8 bit, 1 stop bit and no parity and baud rate of 115200. I am using this protocol to send a command form PC to a specific address in FPGA through hyperterminal. Now I want to read back the content of that address from FPGA back to PC and verify its content. By this explanation, can you give me a hint how to do it?


Thanks and Regards,
 

msdarvishi said:
I defined some signals as registers to stores some values in. I would like to know how is it possible to readback the content of those signals (registers) from FPGA back to PC??
Click to expand...

Given the lack of information in this statement and the lack of clarification from the OP, I suspect maybe they want the hardware equivalent of a printf in C.

Which if so the best solution is vGoodtimes, polled send on state change UART suggestion. If they lack design skills to implement this then using Chipscope (Xilinx SignalTap equivalent) to monitor the registers would work. Note, adding a signal that pulses high on state change would be advisable so that you can use that as the capture qualification in Chipscope.
 

ads-ee said:
Given the lack of information in this statement and the lack of clarification from the OP, I suspect maybe they want the hardware equivalent of a printf in C.

Which if so the best solution is vGoodtimes, polled send on state change UART suggestion. If they lack design skills to implement this then using Chipscope (Xilinx SignalTap equivalent) to monitor the registers would work. Note, adding a signal that pulses high on state change would be advisable so that you can use that as the capture qualification in Chipscope.
Click to expand...


I explained what I want to do in my previous comment for you !
I am sending a command via UART from PC to a specific address in FPGA and now I want to read back the content of that address from FPGA to PC. That's all... is it possible through activation of another UART (I have 2 uart ports on my board) or JTAG interface?
 

msdarvishi said:
I explained what I want to do in my previous comment for you !
I am sending a command via UART from PC to a specific address in FPGA and now I want to read back the content of that address from FPGA to PC. That's all... is it possible through activation of another UART (I have 2 uart ports on my board) or JTAG interface?
Click to expand...

This statement and your original don't say the exact same things (understandable as it's unlikely English is your primary language). This now explicitly states the PC->FPGA connection is used to send commands to the registers (updating them?) and you want to read those registers later FPGA->PC.

Probably less headache to use both UART ports. One is the command/status port, send commands, read/write register, etc. You can have 256 separate commands, or beak it into fields and have less commands with some commands having an address field. e.g. 5-bit command+3-bit address. Then use the other UART to transfer the data bytes write/read
 

ads-ee said:
This statement and your original don't say the exact same things (understandable as it's unlikely English is your primary language). This now explicitly states the PC->FPGA connection is used to send commands to the registers (updating them?) and you want to read those registers later FPGA->PC.

Probably less headache to use both UART ports. One is the command/status port, send commands, read/write register, etc. You can have 256 separate commands, or beak it into fields and have less commands with some commands having an address field. e.g. 5-bit command+3-bit address. Then use the other UART to transfer the data bytes write/read
Click to expand...



AGREE with you ! my original explanation was not enough clear !

Do you mean that using only 1 UART port will solve the problem at the expense of a latency which is not important in my case?
If I want to read back a content of an address from FPGA --> PC, how should I configure it?

Thanks and Regards,
 

I was suggesting using both UARTs one specifically with command information e.g.:
write command (00000) at address (000): 0x00
read command (00001) at address (010): 0x0a
etc...

and a separate data UART.

If I want to read back a content of an address from FPGA --> PC, how should I configure it?
Click to expand...
Uh, I'm not designing this for you. You're supposed to be designing it. Come up with a protocol to handshake the transfer, either using a single UART or both, but you have to either find a standard solution (which I've never seen) or just make one up.

One option is to just have a data FIFO in the FPGA connected to one UART and send the bytes to that UART from the PC for writes. The other UART1 is used to determine where the bytes that are now stored in the UART2's FIFO go using the decoded command and address fields.
Reads do something similar, send the read commands and they get stuffed into the UART2 transmit FIFO and are sent to the PC.

Of course I just made this protocol up in the last 5 min, so it might be rubbish. ;-)

- - - Updated - - -

ARRGH, dpaul wish I'd notice this duplicate thread S**T earlier.

USE THE SEM CORE FROM XILINX. The example design generated already has a protocol for this command interface. The SEM core reads frames in error, you might be able to latch onto the ICAP to separately capture the frames as they get read out, but most of that core is made up of encrypted files. Once you've captured a frame (in a FIFO?) you can send it out a UART.

You do know that using the SEM and accessing the FPGA configuration frame data is..an EXTREMELY ADVANCED FPGA topic.
 

ads-ee said:
I was suggesting using both UARTs one specifically with command information e.g.:
write command (00000) at address (000): 0x00
read command (00001) at address (010): 0x0a
etc...

and a separate data UART.

Uh, I'm not designing this for you. You're supposed to be designing it. Come up with a protocol to handshake the transfer, either using a single UART or both, but you have to either find a standard solution (which I've never seen) or just make one up.

One option is to just have a data FIFO in the FPGA connected to one UART and send the bytes to that UART from the PC for writes. The other UART1 is used to determine where the bytes that are now stored in the UART2's FIFO go using the decoded command and address fields.
Reads do something similar, send the read commands and they get stuffed into the UART2 transmit FIFO and are sent to the PC.

Of course I just made this protocol up in the last 5 min, so it might be rubbish. ;-)

- - - Updated - - -

ARRGH, dpaul wish I'd notice this duplicate thread S**T earlier.

USE THE SEM CORE FROM XILINX. The example design generated already has a protocol for this command interface. The SEM core reads frames in error, you might be able to latch onto the ICAP to separately capture the frames as they get read out, but most of that core is made up of encrypted files. Once you've captured a frame (in a FIFO?) you can send it out a UART.

You do know that using the SEM and accessing the FPGA configuration frame data is..an EXTREMELY ADVANCED FPGA topic.
Click to expand...



@ads-ee,

I previously used SEU controller core (the same as SEM, SEM exists in higher versions) to send commands to a specific address. I am not sure it is useful to read back the content of those addresses again via SEU controller?!
 

The SEM exist(s|ed) for the 5, 6, 7, ultra parts not sure about where the SEU fits in (never even heard of it before). As the SEM uses the ICAP to access the configuration frames it also can read the frames so you can add some middleman logic to capture the reads as they occur.
 

How to readback a regidter content from FPGA to PC using UART?

Hello,

I am using ISE 14.7 targeting a Virtex-5 FPGA board...

There are two 2-wire RS-232 serial port, one with a DB9F connector and one with a three-pin 100-mil header connector (including RX, TX, and GND).

I already used the UART with DB9F to send commands from my PC to FPGA. So, in this configuration, I have the following modules in my top file:

From PC --> To FPGA
The arrows show the sequence of modules connection


HTML: 
Here is my PC        uart_rx pin ------> UART_RECEIVE -------> RECEIVE_FIFO ------       Here is FPGA
                                 
          ---------------------> TRANSMIT FIFO --------------------> UART_TRANSMIT -------------> uart_tx pin



Now, I want to use the second UART connector (3-pin 100-mil) in order to readback the content of a register from FPGA back to my PC. I think I have to configure the 2nd UART port as follows:



HTML: 
 Here is FPGA [/COLOR][/B]      uart2_tx  ---------> TRANSMIT_FIFO ---------> UART_TRANSMIT -----    Here is my PC

                                             UART_RECEIVE ----------> RECEIVE_FIFO ------------> uart2_rx



Am I right?? It seems that for reading back from FPGA to PC, the rx and tx pins must be inversed as well as the FIFO and transmit/receive modules...!

I thank in advance for kind helps and assists.


Regards,
 

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