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CFI Parallel Flash interface in Verilog

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E.amal

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I am working on an Intel’s CFI-Flash (28F640J3) interface in Verilog.
I have written a code and tested it for many commands; read, write, erase.. .
But I am facing problem with 'Write Buffer’ and read process, the command procedure is as follows:
At first I send an "Unlock Block" command then "ERASE BLOCK" then "WRITE BUFFER" then “BUFFER COUNT" which is 16(0X0F) and then I send the data with addresses until 16 count.

When I read the stored data on the LED display and on debugger the read output data comes right for single buffer read-write process starting from address 0 to F.
However, when writing two buffers or more and trying to read them continuously the flash outputs the first 16 words and gives 0XFF for all higher address.
Also, the data of address 0x00 should be 0x00, instead, it was 0xff.
Any hint please.
Thank you.
 

E.amal said:
Any hint please.
Thank you.
Click to expand...

Here is a hint, the problem is in your code. :)

Seriously, nobody will help you unless you post code. Even with code you might not get any help depending on what your code looks like and whether or not anyone can easily understand what you are doing (hint hint, there better be useful comments in the code).
 

ads-ee said:
Here is a hint, the problem is in your code. :)

Seriously, nobody will help you unless you post code. Even with code you might not get any help depending on what your code looks like and whether or not anyone can easily understand what you are doing (hint hint, there better be useful comments in the code).
Click to expand...

Thanks for your reply.
here is the main state machine to interface with CFI-controller
Code Verilog - [expand]
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always @(posedge clk_25M) begin
    if(!RST) begin
        read_cnt <= 1;
        WR2_flash_Addr_cnt  <= WR2_Start_Addr;
        WR1_flash_Addr_cnt  <= WR1_Start_Addr;
        state               <= `idle;
        flash_ctrl_cmd      <= 0;
        FLASH_data_direction <= 0;
        delay_start <= 0;
    end
    else begin      
        case(state)
            `idle: begin
                flash_ctrl_cmd <= 0;
                state <= `flash_write;
            end
            
            `flash_write: begin
                if ((!flash_busy) || flash_ack_o) begin //checks if the flash is in idle state or in acknowledge from write process
                    FLASH_data_direction <= 0;          //for read/write bus address switching
                    flash_ctrl_cmd <= `flash_ctrl_cmd_WRITE;
                    if ( ( WR2_flash_Addr_cnt < WR2_Max_Addr )  &&  flash_dat_i_req) begin  //flash_dat_i_req to tell when to send the address to avoid jumping over address 0
                            WR2_flash_Addr_cnt <= WR2_flash_Addr_cnt + 1 ;
                        end else begin
                            WR2_flash_Addr_cnt <= WR2_Start_Addr;
                            state <= `flash_read;
                    end 
                end 
            end
            `flash_read: begin
                if ((!flash_busy)|| flash_ack_o ) begin
                    flash_ctrl_cmd <= `flash_ctrl_cmd_READ; 
                    FLASH_data_direction <= 1;
                    if ( ( WR1_flash_Addr_cnt < (WR1_Max_Addr) )  && get_read_address ) begin
                    end else  begin 
                        WR1_flash_Addr_cnt <= WR1_Start_Addr;1;
                    end  
                end
                    if (dat_o_rdy ) begin
                            LED_out <= LED_out_o;
                            state <= `read_delay;
                        end
            end
            `read_delay: begin
                if (!delay_busy) begin
                    delay_start <= 1;   
                end else if (delay_finish) begin
                    delay_start <= 0;
                    state <= `flash_read;
                end
            end
            
            default:
                    state <= `idle;
        endcase 
    end // end else
end // end always
                
assign  flash_adr_i = FLASH_data_direction? WR1_flash_Addr_cnt: WR2_flash_Addr_cnt; 
assign flash_dat_i = flash_adr_i[15:0];
    
cfi_ctrl flash1( 
    .sys_rst(oRST_0),
    .flash_clk(clk_25M),
    .ctrl_bus_adr_i(flash_adr_i),
    .ctrl_bus_dat_i(flash_dat_i),
    .ctrl_bus_dat_o(flash_dat_o),
    .ctrl_cmd_i(flash_ctrl_cmd),
 
    .req_done_o(flash_ack_o),
    .busy_o(flash_busy),
    .data_in_clk(flash_dat_i_req),
 
    .flash_dq_io(flash_dq_io),
    .flash_adr_o(flash_adr_o),
    .flash_ce_n_o(flash_ce_n_o),
    .flash_oe_n_o(flash_oe_n_o),
    .flash_rst_n_o(flash_rst_n_o),
    .flash_we_n_o(flash_we_n_o),
    .buffer_write_complete(buffer_write_complete_o),
    .LED_out (LED_out_o),
    .data_o_ready(dat_o_rdy),
    .get_read_addr(get_read_address)
);
 
Last edited:

How about the cfi_ctrl module? If it's existing IP, there should a user manual.
 

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