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Start with the first tick of clock

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ustinoff

ustinoff

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In the picture, the countdown begins from the second tick of the CLK signal. It's very predicteble result if your desing works on "rising_edge" front:

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity p_test is
port(
   en : in std_logic;
   arst : in std_logic;
   clk : in std_logic;
   dout : out std_logic_vector (3 downto 0)
);
end p_test;
 
architecture arch of p_test is
signal counter : unsigned (3 downto 0);
begin
   process(en,clk)
   begin
      if arst = '1' then
         counter <= (others=>'0');
      elsif (rising_edge(clk)) then
          if en = '1' then
     counter <= counter + 1;
     end if;
     end if;
  end process;
dout <= std_logic_vector(counter);
end arch;


But i want to start counting with the first tick of CLK. I know what i need - low front of CLK (CLK = '0') before EN = '1'. Is there another way?

 

This is one advantage of using rising_edge(clk). you have a transition from 'U' to '1'. Is that a rising edge -- from unknown state to '1'?

I don't know how you defined clk, but you should ensure it is '0' before the first transition to '1'.

the older style, (clk'event and clk = '1') would also "work", but the problem really is that you should have clearly defined edges in the simulation.
 

Add initial values of '0' to your clock and enable signal in your testbench.
 

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