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Detecting 3db power gain vhdl (using unsigned lib)

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rahdirs

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Hi,

I need to calculate 3db power gain. The file uses unsigned library & i cannot change/add signed library as the file is being used by others as well.

I have the power values of the current frame & previous frame (s_power & s_power_d1). The power value is such that (actual value -> -3db, value in vhdl -> +30 ).

So, i have written it as


Code VHDL - [expand]
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if( (s_power - s_power_d1) >= 30) then
 ch_3db_gain <= '1';
else
 ch_3db_gain <= '0';
end if;



But the above code makes ch_3db_gain as '1' at both rising edge (eg: s_power = 60, s_power_d1 = 25 ) & falling edge (eg: s_power = 25 & s_power_d1 = 60). This is because of the unsigned library that is being used. How can i detect it only at rising edge ?

I've thought of modifying it in the following way but not sure if it will work. Will have to check in simulation.

Code VHDL - [expand]
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if( (s_power > s_power_d1) and (s_power - s_power_d1) >= 30) then
 ch_3db_gain <= '1';
else
 ch_3db_gain <= '0';
end if;

 
Last edited:

I need to calculate 3db power gain. The file uses unsigned library & i cannot change/add signed library as the file is being used by others as well.
Sounds confused. Why don't you use ieee.numeric_std library and regular signed data type (or may be ieee.std_logic_arith if you have a passion for outdated VHDL)?

Nevertheless your code should work if the numbers are guaranteed to be positive.
 

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