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verilog-a case statement in analog block

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cnd9

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Hi,

I'm running verilog-a for the first time and trying to get the following code to work:

Code Verilog - [expand]
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analog begin
    if (sIntegral > 0) 
        integrand = V(bj);
    else
        integrand = 0;
    sIntegral = idt(integrand,.5);
 
    $fstrobe(fprt,"%f", integrand);
    $fstrobe(fprt,"%f", sIntegral);

etc.....

The behavior I want to see is, "sIntegral" starts at 0.5 and (if V(bj) is negative), keeps decreasing until int(Vdt) becomes less than zero, at which point I want the integration to stop.

Instead, "integrand" initializes to zero, sIntegral initializes to 0.5, and neither change in the simulation as verified with the strobe statements (even though there is definitely a voltage present).

How can I make the conditional statement re-evaluate at each time step so that the integral/integrand will update?


thank you!
 
Last edited by a moderator:

Hi,

You can add the following statements before analog begin and check
Code: 
initial begin
integrand =V(bj)
sIntegral = 0.5
end

Also please try the following code,
Make integrand as electrical and add the following statement
Code: 
V(integrand) <+ (sIntegral > 0)? V(bj) : 0;
sIntegral = idt(integrand,0.5);

VerilogA executes the statements with "<+" assignment everytime any variable in RHS changes so this should work. Along with initial statement this should work.
I didnt try to verify either of them, but you can give it a try.
 
Last edited by a moderator:

Hi, thanks very much for the reply. In the initial block, should I actually say

"V(integrand) = V(bj)"?

And similarly, for the integral,

sIntegral = idt(V(integrand),0.5)

rather than just using "integral" alone?
 

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