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SystemVerilog assign value to signal

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logari84

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Hi,

I am quite new to SystemVerilog. I want to assign a value to a signal that has a width set by a parameter (CODE_WIDTH). When trying to compile in ModelSim I get the error:
near "'b": syntax error, unexpected BASE, expecting ';' or ','

The line is:
assign memory_code[02] = CODE_WIDTH'b00000011;
where CODE_WIDTH = 8

The code compiles if I change the line to:
assign memory_code[02] = 8'b00000011;

The thing is that I want to have the width of the signal as a parameter.

Thank you in advance.
 

parameters can't be used as the width in a constant like that. A define can be used, but I'm sure that is not what you want to do. ;-)

One option is to do something like this, which is ugly, but works.
Code: 
parameter CODE_WIDTH = 8;
assign memory_code[2] = { {CODE_WIDITH-2{1'b0}}, 2'b11 };
which repeats a 1'b0 CODE_WIDTH-2 times.

I'm usually just lazy and just do
Code: 
parameter CODE_WIDTH = 8;
assign memory_code[2] = 3;
which results in things like "32 bits assigned to 8 bit formal" or something like that, which once I've checked I usually just disable reporting or ignore. Only if I plan on making the file reusable will I go to the effort of my first code sample.
 

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