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[SOLVED] VHDL - Reading and writing a file to a variable path

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wtr

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Hello all,

Here is the scenario.

Some user pulls the design from the git repository.

They now have
$path/$user/known_filestructure/

In VHDL there is 
Code VHDL - [expand]
1

file      out_file     : text open WRITE_MODE is "set_in_stone/results.txt";


Where in the past I have concatenated the writemode string by doing
Code VHDL - [expand]
1
2

signal string set_in_stone "some_path" --where some_path is $path/$user/known_filestructure/
file      out_file     : text open WRITE_MODE is set_in_stone & "result.txt"; -- or words to that effect (wtte)



What I want to know is ....
Using only VHDL is it possible to create a string like "$path/$user/known_filestructure/results.txt" ///SUCH THAT vhdl does variable substitution.

I had thought about writing a script to generate a line inside the file, however this is tedious & I would prefer to keep tcl/python scripting out of the solution.

Unfortunately relative paths cannot be used because the modelsim location whereby the file is executed is unknown. It's all generated using vivado tcl scripts & auto generated do files.

Much appreciated for any suggestions.

Regards,
Wesley
 

Pass in set_in_stone via a generic. Generics can be overriden/set in the tool.
 

wesleytaylor said:
Hello all,

Here is the scenario.

Some user pulls the design from the git repository.

They now have
$path/$user/known_filestructure/

In VHDL there is 
Code VHDL - [expand]
1

file      out_file     : text open WRITE_MODE is "set_in_stone/results.txt";


Where in the past I have concatenated the writemode string by doing
Code VHDL - [expand]
1
2

signal string set_in_stone "some_path" --where some_path is $path/$user/known_filestructure/
file      out_file     : text open WRITE_MODE is set_in_stone & "result.txt"; -- or words to that effect (wtte)



What I want to know is ....
Using only VHDL is it possible to create a string like "$path/$user/known_filestructure/results.txt" ///SUCH THAT vhdl does variable substitution.

I had thought about writing a script to generate a line inside the file, however this is tedious & I would prefer to keep tcl/python scripting out of the solution.

Unfortunately relative paths cannot be used because the modelsim location whereby the file is executed is unknown. It's all generated using vivado tcl scripts & auto generated do files.

Much appreciated for any suggestions.

Regards,
Wesley
Click to expand...

I'm not a VHDL specialist, but I don't recall any pre-parsing done by VHDL that does some kind of variable substitution or even a macro substitution like Verilog's `define. I've used `define for this type of thing before and would write a very simple Tcl script to generate the single line based on some user input. Though I always use a file that is not part of the design file and is just an `include line, so my source file doesn't have to be check out and modified.

You might make it a VHDL generic string and use Tcl to apply a new generic value from the tool's shell. Depending on the tool chain involved it might be automated as a Tcl file that must be run prior to some step of the compilation process (i.e. if you use the GUI), otherwise you can source the Tcl file within your current build script.
 

For example, in modelsim you can override generics when you invoke vsim:

vsim my_testbench -gset_in_stone=$path/$user/known_filestructure/

In Quartus it can be set in the project settings
I dont know enough about vivado to know how to set it - but it's quite a simple features I would be surprised if you couldnt.
 
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    wtr

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So my conclusion is
1. Can't do word replacement in VHDL.
2. Can use generics strings & can manipulate aforementioned generics using commands in modelsim. (so not tool agnostic solution)
 

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