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Simulation problem in 8_bit adder VHDL code

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MSAKARIM

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When i simulated this code of 8-bit adder i get output"UUUUUUUU" when using "carry" as a signal instead of variable. i want to know what is the problem ?
Code: 
entity adder8 is
port(a,b: in std_logic_vector(7 downto 0);
cin:in std_logic;
sum: out std_logic_vector( 7 downto 0);
co: out std_logic);
end adder8;

architecture Behavioral of adder8 is
signal carry:std_logic_vector(8 downto 0);
begin
process(a,b,cin)

begin
carry(0)<=cin;

G1:for i in 0 to 7 loop
sum(i) <= a(i) xor b(i) xor carry(i);
carry(i+1)<= (a(i) and b(i)) or (a(i) and carry(i)) or (b(i) and carry(i));
end loop;

co<=carry(8);
end process;
end Behavioral;
 

You left carry out of your process sensitivity list.
Code: 
process(a,b,cin)

It's read in the process and is therefore required.

- - - Updated - - -

Or if you're lucky and your simulator handles VHDL2008 you can use
Code: 
process(all)
instead.

- - - Updated - - -

barry's suggestion may not work exactly as expected due to the carry(0)<= cin; that exists outside the loop. I imagine it may work in some simulators as the order of the assignments in the loop and the carry(0) might result in the carry(0) assignment occurring before the assignment of sum(0). (BTW I check it in Vivado simulator and it does NOT work)

Besides this the real problem is due to the missing signal in the sensitivity list.
 
The internal carry must be a variable, since a signal is only updated at the end of the process.
The same carry bit variable can be used between all stages, so no vector is needed.

Untested code:

Code VHDL - [expand]
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process(a,b,cin)
variable carry : std_logic;
begin
  carry <= cin;
 
  G1:for i in 0 to 7 loop
    sum(i) <= a(i) xor b(i) xor carry;
    carry <= (a(i) and b(i)) or (a(i) and carry) or (b(i) and carry);
  end loop;
 
  co<=carry;
end process;
 
The internal carry must be a variable, since a signal is only updated at the end of the process.
Click to expand...
That's a possible, but not necessary solution. The original code should simulate well with correct sensitivity list.
It's not required that the carry through all bits in a combinatorial process is calculated in a single simulation cycle.
 
std_match said:
The internal carry must be a variable, since a signal is only updated at the end of the process.
The same carry bit variable can be used between all stages, so no vector is needed.
Click to expand...
Reread the OP's first post, they already tried this with a variable and the know that works. They wanted to know why the signal version didn't work.
 
ads-ee said:
Reread the OP's first post, they already tried this with a variable and the know that works. They wanted to know why the signal version didn't work.
Click to expand...

I read it, and I thought there was a much more fundamental problem than a missing signal in the sensitivity list.
As FvM pointed out to me, it will work but multiple iterations of the process are required every time an input signal is changed.
The code is correct if the sensitivity list is adjusted, but it is very bad for simulation ( = slow).
 
std_match said:
The code is correct if the sensitivity list is adjusted, but it is very bad for simulation ( = slow).
Click to expand...

Yes I know that, but didn't bother pointing it out. I've always written this type of iterative stuff far differently than the way the OP coded it.
 

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