draser
Member level 2
Hello,
i am using synopsys Dc and i get the follow Warning: In design 'master_interface', cell 'B_3' does not drive any nets. (LINT-1).The signals that seems to have no drive(because when i simulate the netlist in modelsim i get errors) are :
data_out: out std_logic_vector (data_width-1 downto 0) ;
RW_out
ut std_logic ;
adress_out: out std_logic_vector (adress_width-1 downto 0);
I cant really understand why,for me it seems every is fine in my code.I drive inputs to these signals...Can someone also tell me how can i see that signals the cell B_3 drive?
i use compile_ultra -clock_gate -no_autogroup command for synthesis
I attach my code,if someone can help i would appreciate.
Thank you.
i am using synopsys Dc and i get the follow Warning: In design 'master_interface', cell 'B_3' does not drive any nets. (LINT-1).The signals that seems to have no drive(because when i simulate the netlist in modelsim i get errors) are :
data_out: out std_logic_vector (data_width-1 downto 0) ;
RW_out
ut std_logic ;adress_out: out std_logic_vector (adress_width-1 downto 0);
I cant really understand why,for me it seems every is fine in my code.I drive inputs to these signals...Can someone also tell me how can i see that signals the cell B_3 drive?
i use compile_ultra -clock_gate -no_autogroup command for synthesis
I attach my code,if someone can help i would appreciate.
Thank you.