A thought about meta-stability

Hello,

Consider clock domain crossing of a single signal without a dual stage synchronizer.
The sampling domain captures the signal just when it changes and the DFF goes meta-stable.

The Q pin of that DFF feeds a large block of combinatorial logic.

Now, the metastability condition "eats" away some of the timing budget that could have belonged solely to the combinatorial logic - essentially decreasing Fmax.

But if we know that our design runs at a VERY low speed or/and the combinatorial circuit is VERY small - we need not worry about meastability in this case.

would you agree ?

The MTBF equation has the clock frequency and data change frequency as part of the denominator, i.e.
MTBF = 1/(Fclk + Fdata + X) see this

So with slow data changes and a slow capture clock the MTBF will be low and hence you're probably correct in assuming that you wouldn't necessarily require a two stage synchronizer. I would probably still use a 1 stage syncrhonizer because you might end up with glitches getting propagated though the combonational circuit if there wasn't enough energy to make the output change state completely and it ends up at the original state.

I know that 3 stage synchronizes are rarely necessary - the paper also mentions it.

But is it safe to assume that the matastability condition gets settled within a single T 99.9999999...% of the time ?

shaiko said:

I know that 3 stage synchronizes are rarely necessary - the paper also mentions it.

But is it safe to assume that the metastability condition gets settled within a single T 99.9999999...% of the time ?

Click to expand...

Metastability is all about probabilities. You can't get to 100%, so it is up to you to decide what number you need.

Note that you MUST use at least a one stage synchronizer if the following logic block drives more than one DFF. Otherwise it can happen that different DFF's sample signals based on different values of the domain-crossing signal. Metastability is not necessary for this to happen, so it must be avoided regardless of the signal and clock frequencies.

This also means that you can route the domain-crossing signal directly to a combinatorial logic block if only one DFF is driven (and if the MTBF calculation is OK). However, this is a very bad design practice since tools can destroy it by doing things like register duplication.

Even if such solutions are statistically OK, a big problem is that you as a designer must document and motivate them. It is normally much less work to always use a two stage synchronizer as a minimum. No review will question it.