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[SOLVED] Verilog experimentation but getting too few ports ERROR

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wtr

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How do delete???

Problem
module euler1 (
clk,
rst,
top,
factor1,
factor2,
sumoffactors,
);​

Modelsim error vsim-3017
Click to expand...

Solution
removal of ,
 
Last edited:

Integer is not the same as a 32-bit vector. I wouldn't use it for 32-bit variables as it may not be a 32-bit variable on a 64-bit system.

Integer is used for indexes in for loops and they are the indices in [31:0] vectors, I never use them as inputs and outputs of a module. Verilog isn't a generic programming language in fact it sort of sucks as a programming language. I use Perl/Tcl/Python for "programming tasks".

FYI Verilog is NOT strongly typed so don't treat it as if it was VHDL. You can assign anything to anything in Verilog with NO errors (though you might get some warnings).

Code Verilog - [expand]
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wire [31:0] my_sum
wire [8*20-1:0] my_vector;
assign my_vector = "This is a valid Verilog assign";
assign my_sum = my_vector +20'h12345;


Even though the string is 30 characters it will still assign to the 20 character (8-bit characters) truncating the upper 10 characters, all you'll get is a warning as it's valid to do this.

Furthermore the my_sum adds a 20-bit vector constant to the 160-bit string (which would be an error in VHDL), but this will just add a 0 extended 20-bit constant to the binary equivalent of the my_vector.

Don't use this bad coding style...All the idiots online keep posting ancient pre 2001 syntax for the port declarations when the 2001 C-style syntax has been supported by every useful tool out there for over a decade!
Code Verilog - [expand]
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// old syntax that makes you look like a dinosaur coder
module euler1 (
  clk,
  rst,
  top,
  factor1,
  factor2,
  sumoffactors,
);
 
input clk, rst;
input top, factor1, factor2;
output integer sumoffactors;

Code Verilog - [expand]
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// syntax that makes you look like a hominid coder
module euler1 (
  input           clk,
  input           rst,
  input           top,
  input           factor1,
  input           factor2,
  output [31:0]   sumoffactors
);


Code Verilog - [expand]
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// A nit-picking observation....
// this is using the logical operator NOT
#5 clk = !clk;
 
// you should use the bitwise operator
#5 clk = ~clk;
 
// I've seen people use the wrong operator to do something like this:
wire [7:0] my_sig;
if (!my_sig) begin
...
 
// thinking they are checking if my_sig is 0. Instead they should have used...
 
// use a reduction OR operation (|) followed by bitwise inversion (~),
// so if all bits are 0 the result of the OR gives 0 and invert that to 1.
if (~|my_sig) begin
 
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