How to generate address of a VHDL code on zynq FPGA

Hi,

When i write a code in VHDL, I want to know in which memory location this code goes and gets stored using Vivado for Zynq. How will i come to know this address location using the tool?

I am designing a RAM and want to specify the start and end location where one can come and store the data. This is why i need to know the address.

I am a bit surprised!
You want to write a VHDL code which will be stored in the Zynq RAM?
Or do you want to write a C code that will be stored in Zynq RAM?

If I am not wrong, Zynq is available as a hard and soft processor core.

Based on guessing what you meant. You have been tasked with designing a Zynq design with the Arm connected to a memory?

If so just use the block design tool and add an arm and a memory, then use the auto connection feature to get those two parts to hook up. There will be a tab that allows you to modify the address map of the processor (changes the address decoding).

Hi... I want to define a buffer in block ram of zynq.. This can be done in HDL using the code shown in the below mentioned link

https://vhdlguru.blogspot.in/2011/01/block-and-distributed-rams-on-xilinx.html

However in my case, in place of ram (address) I want to define exact address ex: ram (0x100 to 0x200) so that people can read and write from my buffer. I want to know how to know the exact address of this buffer.

I already told you how to do that using the Block Desgin tool in Vivado, assuming you were using the ARM to build an SoC design.

The part of the design that determines where a physical RAM is located in a processor's memory space is an address decoder.

If the problem is where is a RAM located in some random design without a processor...The RAM is accessed from address 0 up to the maximum address of the RAM. There is no decoding if the RAM is not part of a larger memory mapped system.

The fabric and BRAMs don't have any addresses to the zynq unless you add an AXI interface and have it do the address decoding.

Hello thanks for your reply.. I want to know what type of RAM should I use from the block design tool..I have a block memory generator, distributed memory generator, MIG generator.... My specifications are that I should be able to read and write from a particular address location at the same time and this should be full duplex 16 bit data input output lines... In the block memory generator, all the fields are greyed out for me. Kindly suggest an appropriate option.

Sunayana Chakradhar said:

Hello thanks for your reply.. I want to know what type of RAM should I use from the block design tool..I have a block memory generator, distributed memory generator, MIG generator.... My specifications are that I should be able to read and write from a particular address location at the same time and this should be full duplex 16 bit data input output lines... In the block memory generator, all the fields are greyed out for me. Kindly suggest an appropriate option.

Click to expand...

This is a new requirement. Maybe you should state ALL of your requirements instead of having to make members guess what those requirements are. If you want a 16-bit wide memory then there is no direct support for that in the Block Design tool. If that is a requirement then you will have to make a custom IP, that will likely result in the IP appearing on the processor bus with only the lower 16-bits available for reading writing, which requires 2x the address space (as the addressing is for 32-bit data, instead of 16-bit data).

But that doesn't answer my original question to you, about whether you are using the ARM (not an embedded Zynq processor as post #6 seems to indicate. Zynq is the device FAMILY) or if you are just creating a design (non-processor based).

If you design isn't a ARM based SoC system, is your design a memory mapped system? (i.e. other devices/memory on the ?master_device? address bus that are mapped to specific address locations. If so you decode the address with something like this (assuming you have some sort of master device generating addresses):


I just couldn't resist this time, but sorry about attempting to answer your question, as my answers so far haven't been as helpful as post #6, I'll refrain from helping you further. :blah:

I will be using zynq FPGA.. In order to generate the address to the IP I create on the FPGA, I will need to link it with ARM as post#6 indicates. Moreover as I told you, if I use block memory generator IP with vivado, I cannot configure it as per my needs (16 data i/o and a bram of a partucular size). Looks like I will need to write a vhdl code for a dual port block ram with 16 bitts i/o and define it for a particular size, repackage ip and link it with Zynq PS finally to get the address mapping. Please correct me if i am wrong in my understanding.

Sunayana Chakradhar said:

I will need to link it with ARM as post#6 indicates.

Click to expand...

I mentioned using the ARM in both posts 3 & 5, but you seem to have ignored my posts.

Moreover as I told you, if I use block memory generator IP with vivado, I cannot configure it as per my needs (16 data i/o and a bram of a partucular size). Looks like I will need to write a vhdl code for a dual port block ram with 16 bitts i/o and define it for a particular size, repackage ip and link it with Zynq PS finally to get the address mapping. Please correct me if i am wrong in my understanding.

Click to expand...

I already told you to do this in post #8, but as you seem to distrust my advice you can certainly wait for someone else to tell you how to do this.