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Doubt in xapp1052 reference design from xilinx

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biju4u90

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I am using xapp 1052 reference design for DMA transfer using PCIE. But I am unable to clearly understand what operations do the RX and TX modules do in the different states of the state machine. Can somebody explain the operations done in each states of the state machine??
 

Be more specific.
What page in the application note does your question refer to ?
 

I am trying to simulate the code. In the code for the RX section, there are states named BMD_128_RX_CPL_STRAD, BMD_128_RX_CPLD_STRAD and BMD_128_RX_CPLD_QWN. I am unable to identify the purpose of those states in the state machine!!
 

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