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error loading design in Model Sim

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moin_moin

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I am learning VHDL by my own and wrote a small program for AND. My program is getting compiled successfully but when I simulate it I get an error message "vsim work.and2 vsim Start time: 20:39:58 on Mar 20,2016 Error loading design" Please help someone help me to solve this problem Thanks in advance.
 

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