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generic default values in vhdl

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Binome

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Hi,
I'm working with someone that is used to use default values in entities with no "generic map" in modules instanciation.
I think this is a bad way of using the generics: you can't reuse the modules with other values and it's difficult to read.
What do you think?
 

Re: Using generics in VHDL modules

Would be a problem if the instantiation is the only available IP documentation. Hopefully it's not.

It's quite common that IP has optional ports and different modes that aren't utilized in a specific design. My preferred way is to omit all unused ports and generics for sake of code readability (as far as they have useful defaults). Both for vendor and own IP.
 

Binome said:
I'm working with someone that is used to use default values in entities with no "generic map" in modules instanciation.
I think this is a bad way of using the generics: you can't reuse the modules with other values and it's difficult to read.
What do you think?
Click to expand...
Unless the generics of the lower level module are brought out as generics of the upper level module, the upper level won't be reusable anyway even if the lower level is instantiated with a 'generic map'.

However, if the only thing needed to make that upper level reusable is to add generics, than add the generics to the upper level module and the generic map at the time when you would like to reuse the module. Until the time that you have an actual need to reuse the upper level module, it doesn't really matter if the module doesn't instantiate lower level modules with generics or not.

Kevin Jennings
 

It depends on the situation:

1. You add a generic that wasn't there before
A default value is good. It should give the same behaviour as the old version without the generic, so you don't break old code that use the entity.

2. Generics with an obvious default value.
One example is a generic that is used in simulation to reduce the simulation time. Maybe by reducing delay times or similar.
The generic can have a default value set for synthesis.

3. Generics without an obvious default value.
One example is a generic to specify a bus width. A default value should be avoided.
This is done the wrong way in System Verilog interfaces. There you MUST have a default value.
 
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