Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Verilog assign &

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hello,

What does this code do?
assign y= & x;
 

'&' is doing a bitwise and operation. i.e. all bits of signal 'x' will be anded with each other and resultant value would be assigned to Y.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
LRM 11.4.9 Reduction operators
Click to expand...
I knew what '&'
What I wasn't familiar with is the single line statement.
 

Assignment operations are mostly single line, isn't it?
 

Sorry, I meant "single argument" - not "single line".
In VHDL unary operators weren't possible before 2008, I didn't know Verilog supports it.
 

Verilog has always supported this unary reduction operator, even my book from '93 (pre-IEEE standardization '95) shows it. VHDL has been slowly copying stuff from Verilog over the years.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top