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Designing a packet processor on the FPGA ZC7020

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Sunayana Chakradhar

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Hello,

I have to design a packet processor on the FPGA ZC7020. I have a buffer, fragmentation unit, framing, parsing etc blocks. My payload size is 9 MB. The data to the buffer comes from a IDT SDRAM which has 16 bits I/O. The buffer has to be as big as to accumulate 500 bytes of packet which is my MTU size. Next it has to send this 500 bytes packet to the Framing unit and so on. My question is that in digital logic, data is sent bit by bit. How can I send the entire 500 bytes between fragmentation unit and framing unit and other blocks in my design in one go as an entire packet? Should i have buffer at every stage (fragmentation, framing, parsing and so on)? Will that not add latency in my design? You can check the attached diagram for more information about the blocks. The URL is here

https://obrazki.elektroda.pl/3189258300_1457712035.jpg

I am unable to get any information regarding this question. Hence this post
 

Packets are streamed at n bits/clock. The logic will track where it is in the packet if it needs to disect headers etc. this is how all digital logic works. It will never send and entire packet "in one go".

The diagram you posted is a very high level data flow diagram. You need to translate this in to a hardware architecture.
 

Yeah so to send 500 bytes suppose it takes 100 clock cycle for example, the fragmentation unit will need to wait and store the previous bits until full packet arrives? Its going to be another buffer then. My fragmentation unit logic needs to decide if the incoming packet is 500 bytes. If it is within 500 ytes, I don't need to fragment. Else if it is more than 500 bytes, I need to fragment. Its something like a comparator.
 

Without knowing what the packets are or what this fragmentation unit is doing, you cannot say for sure what it needs. Maybe it can just forward the data on like normal?
You need to get more specific
 

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