Sunayana Chakradhar
Member level 5
Hello,
I have to design a packet processor on the FPGA ZC7020. I have a buffer, fragmentation unit, framing, parsing etc blocks. My payload size is 9 MB. The data to the buffer comes from a IDT SDRAM which has 16 bits I/O. The buffer has to be as big as to accumulate 500 bytes of packet which is my MTU size. Next it has to send this 500 bytes packet to the Framing unit and so on. My question is that in digital logic, data is sent bit by bit. How can I send the entire 500 bytes between fragmentation unit and framing unit and other blocks in my design in one go as an entire packet? Should i have buffer at every stage (fragmentation, framing, parsing and so on)? Will that not add latency in my design? You can check the attached diagram for more information about the blocks. The URL is here
https://obrazki.elektroda.pl/3189258300_1457712035.jpg
I am unable to get any information regarding this question. Hence this post
I have to design a packet processor on the FPGA ZC7020. I have a buffer, fragmentation unit, framing, parsing etc blocks. My payload size is 9 MB. The data to the buffer comes from a IDT SDRAM which has 16 bits I/O. The buffer has to be as big as to accumulate 500 bytes of packet which is my MTU size. Next it has to send this 500 bytes packet to the Framing unit and so on. My question is that in digital logic, data is sent bit by bit. How can I send the entire 500 bytes between fragmentation unit and framing unit and other blocks in my design in one go as an entire packet? Should i have buffer at every stage (fragmentation, framing, parsing and so on)? Will that not add latency in my design? You can check the attached diagram for more information about the blocks. The URL is here
https://obrazki.elektroda.pl/3189258300_1457712035.jpg
I am unable to get any information regarding this question. Hence this post