Using generics in VHDL modules

Hi,
I'm used to use generics in many VHDL modules but someone told me it's not advisable for big projects.
I don't understand why. I thought generics were to be used every time to make the modules reusable in many projects.
What is your opinion?
Thanks.

Binome said:

Hi,
I'm used to use generics in many VHDL modules but someone told me it's not advisable for big projects.
I don't understand why. I thought generics were to be used every time to make the modules reusable in many projects.
What is your opinion?

Click to expand...

There is absolutely no reason to not use generics regardless of project size. When someone makes such a strange statement it is usually a good idea to ask 'Why?' and, in this case, what is the definition of 'big'.

Kevin Jennings

someone told me it's not advisable for big projects.

Click to expand...

That's an un-contexted vague and overgeneralized statement.

Generics give you the means to configure and parameterize your code - regardless of project size.
Sometimes it's suitable to use them and other times it makes little sense.

For example, hardware like PLLs / CPUs / FIFOs / DDR controllers - have many configurable parameters and will benefit a lot from the use of generics.
On the other hand - a VERY specialized, one time design that has been tailored with precise values that aren't expected to change) will benefit less.

It's what I thought: generics are to be used without any risk. I'm going on with it.
Thank you both.

I'm going on with it.

Click to expand...

Stay brave!

Generics are fine. The main issues are that they are not cross-language and a larger module may have a large number of untested configurations, and possible issues with some build flows.

Basically, VHDL allows more complex generics/ports that don't translate into Verilog. If the code is used in a mixed environment, the ports/generics should make sense for both VHDL/Verilog.

The second is an issue because often it will seem like a problem can be solved simply by incrementing a generic. If the developer never tested for this, then you might uncover unexpected behavior. This is problematic if the developers do not add in assertions for valid configurations as well as valid ranges.

Finally, if the generics are part of a larger module but do not affect port sizes, it is possible to use a version of the netlist that has different generics than the HDL. (for me, I had a project with multiple large modules that were synthesized to netlists in a previous build step. That build step set the generics for the core based on info in a makefile. The port sizes were the same. The result was a design where the implementation did not match the RTL.)