Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how to use multiple port declare in systemverilog?

Status
Not open for further replies.
U

u24c02

Advanced Member level 1
Joined
May 8, 2012
Messages
404
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,101
Dear all,

I'm trying to excercise with some systemverilog example on www.testbench.in of swith example.

But I'm confused in here.

Code: 
output_interface output_intf[4](clock);

testcase TC(mem_intf, input_intf, output_intf);

program testcase (..., output_interface.OP output_intf[4]);

Versus

Code: 
output_interface output_intf[4](clock);

testcase TC(mem_intf, input_intf, output_intf[4]);

program testcase (..., output_interface.OP output_intf[4]);

I'm confused that I think it must be like this.


testcase TC(mem_intf, input_intf, output_intf[4]);​

not

testcase TC(mem_intf, input_intf, output_intf);​

Would you let me know how to use multiple port?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top