kushal nandanwar
Full Member level 3
q<=#10 d;
What this statement do in verilog?
What this statement do in verilog?
Last edited by a moderator:
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In a simulation enviroment - it'll assign d to q after 10 simulation ticks.
Or so I think...
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 module dff8(q,d,clk); input [7:0]d; input clk; output [7:0] q; /* always@(posedge clk) begin*/ assign q= #10 d; /* end*/ endmodule
What if the "clk" signal that triggers the always block is faster than 10 timescales ?It assings Q after 10 `timescale units
As far as I understand - in VHDL one a process is entered (per sensitivity list) and a signal assignment is scheduled - any old scheduled assignments are overridden. This is UNLESS the "transport" keyword is used.The RHS is evaluated immediately, the LHS assigned after the delay, creating a transport delay.