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[SOLVED] Verilog code for 74LS190

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nizdom

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Hi All,

I am a newbie in Verilog and I wanted to make a code to display the functions of the 74LS190 which is an Up/Down Counter. 74LS190 is a synchronous Up/Down BCD Counter in which the state changes of the counter are synchronous with the LOW-to-HIGH transition of the Clock Pulse Input. I wanted to code something like it will count up from 0 to 9 then back to 0 and count down from 9 to 0 then back to 9. Any help? Can you check the code below if it answers my question and if not, any way I can modify the code?
Code Verilog - [expand]
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module up_down_counter    (
 out      ,  // Output of the counter
 up_down  ,  // up_down control for counter
 clk      ,  // clock input
data     ,  // Data to load
 reset       // reset input
  );
//----------Output Ports--------------
 output [9:0] out;
//------------Input Ports-------------- 
input [9:0] data;
input up_down, clk, reset;
//------------Internal Variables--------
reg [9:0] out;
 //-------------Code Starts Here-------
always @(posedge clk)
if (reset) 
   begin // active high reset
     out <= 10'b0 ;
   end else 
       if (up_down) 
          begin
             out <= out + 1;
          end else 
              begin
                  out <= out - 1;
              end
endmodule
 
Last edited by a moderator:

nizdom said:
Can you check the code below if it answers my question and if not, any way I can modify the code?
Click to expand...

You need to make the testbench to perform simulations.
It is part of the job when coding in hdl languages.
 

andre_teprom said:
You need to make the testbench to perform simulations.
It is part of the job when coding in hdl languages.
Click to expand...

I am using the Quartus II 9.0 Web Edition so no testbench is required as it is already has simulation. What can you say about the code?
 

nizdom said:
I am using the Quartus II 9.0 Web Edition so no testbench is required as it is already has simulation.
Click to expand...

Quartus II has a visual interface to make easy you draw the stimuli signals, but it is actually saved within a file in the same language set as the default in project. Regardless, the simulation is that will allow you determine whether it's working properly or not.

nizdom said:
What can you say about the code?
Click to expand...

I didn't see where in the code you ensure that conting will not exeed 9.
 

andre_teprom said:
Quartus II has a visual interface to make easy you draw the stimuli signals, but it is actually saved within a file in the same language set as the default in project. Regardless, the simulation is that will allow you determine whether it's working properly or not.



I didn't see where in the code you ensure that conting will not exeed 9.
Click to expand...

Hi, can you check the code below? I wanted to make an up/down counter that will count up from 0 to 9 then back to 0 and/or count down from 9 to 0 then back to 9. 

Code Verilog - [expand]
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module updown(data_in, clk, enable, dwn_up, load, data_out, ripple, max_min);
 
input [3:0]data_in;
input clk;
input enable;
input dwn_up;
input load;
 
output [3:0]data_out;
output ripple;
output max_min;
 
wire clk, 
     enable,
     dwn_up,
     load;
    // [3:0]data_in;
 
 
reg [3:0]data_out,
    max_min,
    ripple;
 
 
always@(posedge clk)
 
begin    //1
  if (load==1)                                        // checks if program mode is on
    begin //2
      if(enable==0)                                   // will count if enable is low otherwise counter will pause
        begin  //3
           if(dwn_up==0)                              //checks if count up
             begin   //4
              if(data_out==4'b1111)                     //overflow
                begin  //5
                  data_out<=4'b0000;                    //reset
                  max_min<=1;  
                  #10 ripple<=0;
                end    //5
              else
                begin    //6
                  data_out<=data_out+1;                //not overflow
                  max_min<=0;
                  ripple<=1;
                end       //6
             end      //4
           else                                       // else counter will count down
             begin     //7
              if(data_out==4'b0000)                    // check for underflow
                begin    //8
                  data_out<=4'b1111;                    //reset
                  max_min<=1;
                  #10 ripple<=0;
                end      //8
              else                                   //no underflow and counter counts down normaly
                begin    //9
                 data_out<=data_out-1;
                 max_min<=0;
                 ripple<=1;
                end      //9
             end       // 7
        end      //3
      else                                             // enable is 1 thus counter pauses
        data_out<=data_out;
    end    //2
  else                                                //program mode is on
    data_out<=data_in;
end     //1
 
endmodule
 
Last edited by a moderator:

nizdom said:
can you check the code below?
Click to expand...

It sounds as if you had disregarded the previous recommendation to yourself make the simulation to check the working of code. Did you at least compiled this code ? Taking a quick look did not seem to be anything out of place I but could be wrong; anyway the code lenght certainly could be reduced by using simpler implementations ( e.g reloading data_out variable at overflow/underflow, I guess ). In addition, once it has in lines 38 and 53 a time dependent statement #, it is assumed it will work only in simulation environment, right ?
 

I did simulate the code and it run with no errors. The code above was for 74LS191 and I wanted to modify it because I wanted to implemet 74LS190. When I simulated the code, it counted from 0 to 15. What I wanted to make is after 9, it will go back to 0. What do you think shall I do with code to do this?
 

You should modify the statement :

Code: 
if(data_out==4'b1111)

replacing by :

Code: 
if(data_out==4'b1010)
 

After analyzing the code, I did the same thing in what you recommended. Thank youuu. :clap:
 

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