Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VHDL - purpose of the "group" keyword

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hello,

What is the purpose of the "group" keyword in VHDL ?
 

Apparently its for a "collection of types that can get an attribute"
Ive never used it, or seen it used. Like you, the first time I saw it was in vGoodTimes' post.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
I can't find too many example of it either.
VHDL is getting C++thesized...
 

What do you mean by C++ thesized?
VHDL hasnt changed much fundamentally since 1987.
 

Group is an old feature, introduced in VHDL 1993. I also never used it. Perhaps someone can give an example of an useful application.
 

Re: VHDL - purpose of the "group" keyword

I saw it in some random website that listed VHDL keywords, but without any useful use-cases listed. The use-case I came up with was for applying attributes to a group of signals.

eg, if you have two or more attributes to apply to a group of signals (or labels, or etc...) you should be able to declare a group and then apply the attributes to the groups. This avoids the copy/paste of signals*attributes.

When I tried it, it did not work because "group" was not a recognized reserved word in the synthesis tool.

- - - Updated - - -

In terms of C++ influence on VHDL/SystemVerilog, I think this is a good thing.

VHDL2008 added type generics. This is similar to C++ template functions/classes that can take a type as an argument. I don't think functions can return types just yet, but I'm not 100% sure on that. I've always wanted pure functions to be able to return types or subtypes.

SystemVerilog has interfaces, which include data members and functions/tasks acting on the data members. Similar to the most basic C++ objects.



There is already a lot that can be done to "C++"ize your code without using the newest standards. Procedures, used in a thoughtful manner, are amazingly useful and nearly the best kept secret in VHDL. But there is a fairly strong bias against them.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
SystemVerilog has interfaces- but they are a little impotent (polymorphism on an interface would be useful!)- but no more than VHDL. Classes would be very handy in VHDL - and they kind of went half way to implementing them with protected types, and then the ability to put generic types and generics on packages (so you can almost use a package like a class), but not quite full classes. Its kind of killed off VHDL as a full featured language.
 

What's a "protected type" ?
 

Re: VHDL - purpose of the "group" keyword

protected types were introduced with VHDL 2002. They are types that contain their own member variables, functions and procedures. Also, in 2002, any shared variables must be a protected type. They look similar to classes, but no inheritance is possible, you cannot have a pointer to a protected type and you cannot have an array of protected types, which is rather annoying.

Here is an example:

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

type mem_model_t is protected
  type mem_t is array(0 to 255) of std_logic_vector(7 downto 0);
  variable mem : mem_t;
 
  function std_logic_vector read(addr : integer range 0 to 255) is
    return mem(addr);
  end function;
 
  procedure write(d : std_logic_vector(7 downto 0); addr : integer range 0 to 255) is
    mem(addr) := d;
  end procedure;
 
end protected mem_model_t;
 
 
shared variable mem_model : mem_model_t;
.......
 
 
process
begin
  input <= mem_model.read(N);
 
  ......
 
   mem_model.write(N, output);
end process;


- - - Updated - - -

And here is a more complex example, showing the power of them (with some 2008 features thrown in)

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111

package ll_test_pkg is
    generic (
        type data_t;
        NULL_VALUE  : data_t
    );
 
    type link_list_t is protected
        procedure add_item( d : data_t );
        impure function get_item return data_t;
    end protected link_list_t;
 
end package ll_test_pkg;
 
 
package body ll_test_pkg is
 
    type link_list_t is protected body
        type data_ll_t;
        type data_ll_ptr_t is access data_ll_t;
 
 
        type data_ll_t is record
            d       : data_t;
            d_next  : data_ll_ptr_t;
        end record data_ll_t;
 
        variable start  : data_ll_ptr_t;
 
        procedure add_item( d : data_t ) is
            variable ptr    : data_ll_ptr_t;
        begin
            ptr         := new data_ll_t;
            ptr.d       := d;
            ptr.d_next  := start;
 
            start       := ptr;
 
        end procedure add_item;
 
 
        impure function get_item return data_t is
            variable ret    : data_t;
            variable ptr    : data_ll_ptr_t;
        begin
 
            if start /= null then
                ret     := start.d;
                ptr     := start.d_next;
 
                DEALLOCATE(start);
 
                start   := ptr;
            else
                ret     := NULL_VALUE;
            end if;
 
            return ret;
        end function get_item;
    end protected body link_list_t;
end package body ll_test_pkg;
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use std.textio.all;
 
entity ll_test is
end entity ll_test;
 
architecture sim of ll_test is
 
begin
 
    process
        package ll_test_us_pkg is new work.ll_test_pkg
        generic map (
            data_t      => unsigned(7 downto 0),
            NULL_VALUE  => x"XX"
        );
 
        package ll_test_int_pkg is new work.ll_test_pkg
        generic map (
            data_t      => integer,
            NULL_VALUE  => -1
        );
 
 
        variable ll_us      : ll_test_us_pkg.link_list_t;
        variable ll_int     : ll_test_int_pkg.link_list_t;
 
    begin
        ll_us.add_item( to_unsigned(6 , 8) );
        ll_us.add_item( to_unsigned(10, 8) );
        ll_us.add_item( to_unsigned(12, 8) );
        ll_us.add_item( to_unsigned(21, 8) );
        ll_us.add_item( to_unsigned(31, 8) );
 
        for i in 1 to 5 loop
            ll_int.add_item( to_integer( ll_us.get_item) );
        end loop;
 
        for i in 1 to 5 loop
            --write(OUTPUT, to_hstring( ll_us.get_item ) & LF );
            write(OUTPUT, to_string( ll_int.get_item ) & LF );
        end loop;
 
        wait;
   end process;
end architecture sim;
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top