[SOLVED] Quartus II synthesis warning

I am having issues with my design when performing synthesis in Quartus II. The synthesis gives me these two warnings:

Warning (13024): Output pins are stuck at VCC or GND
Warning (21074): Design contains 203 input pin(s) that do not drive logic

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The first warning includes all the outputs of the top-level module. And the second warning includes all the inputs of the top-level module. I have assigned all the input/output pins in the Pin Planner(so as not to leave any pins hanging). I am still unable to get rid of these warnings. And due to these warnings the synthesis generates 0 logic elements. I completed the entire compilation process (despite these warnings) and have run an RTL simulation with a testbench that I wrote and the simulation seems to work perfectly. However, as I assume the design is not synthesizing correctly.

Please help me rectify any issues in my code.

Thanks

As i can see, your assigned pins are not actually driving logic elements. If the simulation seems to work perfectly it might be that your code is able to be simulated but not implementable due to deficiencies in HDL coding and this is a common issue for HDL beginners. If you have done previous working codes then please try to look out if your signals are mapped to the instantiated components.

The first warning includes all the outputs of the top-level module. And the second warning includes all the inputs of the top-level module.

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However, as I assume the design is not synthesizing correctly.

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A reasonable guess. This happens if the design is completely functionless according to the analysis performed by Quartus. This can have trivial reasons, e.g. clock, reset or signal connections are missing.

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As i can see, your assigned pins are not actually driving logic elements.

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I can't confirm at first sight (Or may be I just didn't see it).
It's also not understandable how the RTL simulation would give reasonable results in case of missing design connectivity (unless you have forced variables, etc.). I presume something has changed between simulation and synthesis.

To check the design function, we would need the instantiated module's code, too.

If you have done previous working codes then please try to look out if your signals are mapped to the instantiated components.

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I have previous versions of the code. In one such working version, all the other connections are same except for the N_slice and N_out connections. Instead I just had one input [NLEN:0] N. Those versions seemed to synthesize perfectly with the rest of the instantiated sub-modules being the same as this version.