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Super confused with LUTs and MUX

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loic88

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Hello all,

Being more specialised in ASIC design, I decided today to take a look at FPGA design, and I am super confused by a question I have seen:

"What will be the maximum size of a multiplexer if I have a 6 inputs lookup table?"
Click to expand...

In my head, a 6 inputs lookup table is "by definition" a 64 -> 1 MUX, as for each combination of input bits you can define an output. (the 6 bits are then selection bits)....

How would you answer this?
 

It depends what the values connected to the muxes are.
If the values are all constant from a 6 bit select line, then yes.
If not, ie. you need to mux dynamic signals A,B,C,D, then the largest Mux you can implement with a 6 input lut is a 4-1. 2 input select lines and 4 variable inputs.

- - - Updated - - -

I guess - in the strictest sense, you could argue that in fact, my 2nd option is really only the first one.
But from a more abstract circuit design POV, it's not a 64-> mux.
 

Ha I guess I got really confused as your answer is quite simple, and it really makes sense.

Thank you :wink:
 

If not, ie. you need to mux dynamic signals A,B,C,D, then the largest Mux you can implement with a 6 input lut is a 4-1. 2 input select lines and 4 variable inputs.
Click to expand...
Can you post an example of this LUT.
 

shaiko said:
Can you post an example of this LUT.
Click to expand...

Code: 
process(a, b, c, d, sel_bits)
begin
  mux_out <= a when sel_bits = "00" else
             b when sel_bits = "01" else
             c when sel_bits = "10" else
             d when sel_bits = "11" else
             'X';
end process

6 input bits and one output bit, perfect for one 6-input LUT.
 
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    shaiko

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I didn't mean the VHDL code.
I meant the LUT that this code gets synthesized to...
 

shaiko said:
I didn't mean the VHDL code.
I meant the LUT that this code gets synthesized to...
Click to expand...

I am not sure I understand what you want. A 6-input LUT is only a 64 x 1 bit RAM initialized to give the correct output. All 6 inputs are used as address lines.
The hardware inside the FPGA will be identical if you instantiate a ROM64X1 with the proper contents.
Do you want to see the memory contents?
 

The memory contents will depend on which inputs are considered to be the select inputs.

The mux can also be written as x"FF00F0F0CCCCAAAA"

In binary with the inputs shown:

XYDCBA O-- Let the two highest bits "XY" be the select inputs, DCBA are the inputs, O is the output

000000 0 -- Select bits = "00", let the output follow the "A" input
000001 1
000010 0
000011 1
000100 0
000101 1
000110 0
000111 1
001000 0
001001 1
001010 0
001011 1
001100 0
001101 1
001110 0
001111 1
010000 0 -- Select bits = "01", let the output follow the "B" input
010001 0
010010 1
010011 1
010100 0
010101 0
010110 1
010111 1
011000 0
011001 0
011010 1
011011 1
011100 0
011101 0
011110 1
001111 1
100000 0 -- Select bits = "10", let the output follow the "C" input
100001 0
100010 0
100011 0
100100 1
100101 1
100110 1
100111 1
101000 0
101001 0
101010 0
101011 0
101100 1
101101 1
101110 1
101111 1
110000 0 -- Select bits = "11", let the output follow the "D" input
110001 0
110010 0
110011 0
110100 0
110101 0
110110 0
110111 0
111000 1
111001 1
111010 1
111011 1
111100 1
111101 1
111110 1
111111 1​
 
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