Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Full Camera Link Full - Multiple Clocks

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hello,

The full Camera Link standard allows a pixel size of up-to 64 bits.
These 64 bits (of the same pixel) are negotiated over 3 aggregated groups (24,24,16 bits).

However, each group has it's own pixel clock (giving us 3 clocks)...So how does the receiving side know how to re-aggregate the data of a specific pixel if each bit group has it's own clock ?
In other words, what prevents the receiver from erroneously mixing data from pixel n with data from pixel n+1 (or n-1) ?
 

shaiko said:
So how does the receiving side know how to re-aggregate the data of a specific pixel
Click to expand...
Just guessing, but considering that each group has its own clock, would be expected its own PLL on receiver side, so once the frame size is well defined, the completion of each bunch should occur separately.
 

You need to map the bits according to this page : https://en.wikipedia.org/wiki/Camera_Link. In fact, you can pack more than one pixel in a 64 bit. In the past, I packed 4 pixels of 16 bits for each clock cycle of 80MHz, i was sending 4 pixels at a time.

For this you need to use ioserdes 7:1.

To keep synchronisation, the receiver needs to use FVAL (Frame Valid), LVAL (Line Valid) and DVAL (Data Valid). The frame grabber needs to know what is the format you used to display the information correctly.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
So you used fifos for the phase alignment and a state machine that monitors the frame and line signals?
 

After packaging the pixels to form a 64 bits vector I stored them in a FIFO to have a complete line. When the fifo got enough pixels to form a line, I sent them to the frame grabber.

I never did the receiver side but I presume that they store the pixels that has the FVAL, LVAL and DVAL valid. If one them is not valid they simply ignore the pixels.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top