Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Vivado tcl scripting

Status
Not open for further replies.

vahidsh

Newbie level 6
Joined
Feb 2, 2015
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
117
Hi dear all,
I have a question about tcl scripting in vivado.
I can not understand why most designer use tcl scripting in vivado?? Where using tcl scripting is useful?(for example all command like "add_bp" or "get_design or ... Seems useless in order of design complexity!!!)
And when it is recommanded to use tcl scripting?
Thank you all.
 

One benefit is the tool not unloading the design every time you perform a new operation.

GUI
Read RTL, Elaborate design, unload design database, load design database, Synthesis, unload design database, load design database, implementation, unload design database, load design database, bitstream generation, unload design database.

Tcl
Read RTL, elaborate, synthesis, implementation, bitstream generation.

On the same design the Tcl version runs much faster, you would have to run with the GUI version on an SSD to get reasonably close to the speed of the TCl version, which never unloads the design unless specifically directed.
 

One reason given by the Xilinx FAEs:
"The non project flow has more options than the project flow"
"Non project flow is primarily run via tcl"
"the gui usually runs project flow".
"we recommend non-project flow"

So use tcl.
 

I just admire the clarity and power of the batch mode work flow. The difference can only be felt by someone who has worked with both flows.
I would always recommend the TCL flow. However initial design creation with TCL flow takes a little more time than the project flow (I guess most bosses are generous enough to grant that extra time ;-)). But for an experienced engineer I think that this time is only marginally more.
 

Thank you

Could you please give some usefull command that you usually use ?

Yes exactly i am newly to use tcl commands and i want to learn some commands that is very very usefull ( in saving time ) .

Thank you again.
 

No one command is any more useful than any other. You just need ty learn the commands you need for your situation.

Tclsh myproject.tcl
 


Just one hint. When you use the GUI to implement your design in vivado, take a look at the TCL console. All commands are printed there and you can copy paste them in a TCL script to run later.
 

Thank you for your answers dear frinds...
I have another question:
I want for example change my dcp file or running strategy during runing synthesis or implantation if there is a slack less than 0 . So if there is a slack less than 0 i want change my running strategy. I want do this task automatically( tcl scripting ) . Is it possible for example write " if (any slack<0) then "launch synth_2" or something else in tcl to detect slack and then change running strategy?
 

Most design compilers perform timing driven synthesis up to a certain extent. In so far they are already doing what you want to achieve. A limit is at the point where you need to change the rtl description (e.g. insert pipeline stages) to improve timing. I doubt that scripting can help much in this regard.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top