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How to implement UART in UTLP

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Shreenivasa

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Im working on a project in UTLP kit where i need to implement UART. The following code is perfectly transferring single character. The problem is im not able to find out the way to send sting of charcters like"AT+CMGF=1".
please help me out
Code Verilog - [expand]
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module char_1(clk, txd, reset);
 
input clk,reset;
output txd;
 
 
reg [10:0] tx_baud; // Send Baud Rate Timer
reg [9:0] tx_buff; // Transmit buffer
reg [10:0] send_data;
 
 
/* Transmit baud rate */
always @ (posedge clk or posedge reset)
if (reset ==1'b1)
tx_baud <= 11'h000;
else if (tx_baud == 11'h411)              10M/9600=1042
tx_baud <= 11'h000;
else
tx_baud <= tx_baud + 1'b1;
 
/************** Shift register transmitted once ****************/
always @(posedge clk or posedge reset)
if (reset ==1'b1)
tx_buff <= (send_data << 2) | 10'b0000000001;
else if (tx_baud == 11'h411)
begin
tx_buff[0] <= tx_buff[1];
tx_buff[1] <= tx_buff[2];
tx_buff[2] <= tx_buff[3];
tx_buff[3] <= tx_buff[4];
tx_buff[4] <= tx_buff[5];
tx_buff[5] <= tx_buff[6];
tx_buff[6] <= tx_buff[7];
tx_buff[7] <= tx_buff[8];
tx_buff[8] <= tx_buff[9];
tx_buff[9] <= 1'b1;
end
 
assign txd = tx_buff[0];
 
always @ (posedge clk or posedge reset)
begin
send_data <= "A";
end
 
endmodule
 
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 
Last edited by a moderator:

Shreenivasa said:
The following code is perfectly transferring single character. The problem is im not able to find out the way to send sting of charcters like"AT+CMGF=1"
Click to expand...
Why not implementing a state machine for addressing each character of that string ?
 

I repeat what Andre has said.
A good UART design will always implement a state machine. It is advisable to change your UART design.
 
In hierarchical design, it's O.K. that the UART module processes single characters. But to be able to send multiple characters sequentially, it must be supplemented with a start trigger and a busy signal. You'll surely realize that the UART module needs at least a bit counter to implement these signals.
 
Sir,
Is it possible to give a sample verilog code that transmits and receives multiple characters using state machine method?
 

I did a google search for "verilog code uart" and it showed 123,000 results.
 

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