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if i want to wait for 1 clk period

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sai685

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I have a address phase and a dataphase . But what i want to do is get the dataphase after one clock period of address phase in the result so what i have to do.
1 In ahb protocol in the first phase the address is sampled
2. In the second phase the data is sampled .
so for getting data in the next phase what i have to do. that means i want to create a wait state for 1 clk period.
 

There is no information given about the processor, programming language, program, etc. so, it's difficult to give a useful answer.
On some microcontrollers, a "NOP" instruction will use up one clock cycle.
 

FenTrac said:
There is no information given about the processor, programming language, program, etc. so, it's difficult to give a useful answer.
On some microcontrollers, a "NOP" instruction will use up one clock cycle.
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APB isn't software, it's a hardware on chip bus. So a NOP instruction won't help. Either VHDL or Verilog will be used to design the logic. You do have the ARM IHI 0024 "AMBA APB Protocol Specification"?

You detect the address phase using PSEL and the write phase using PENABLE and use that to generate an enable for the register capturing the data during the data phase. You assert PREADY when the write or read has finished inserting wait states (which merely means you don't change the state of the signals on the bus).

This is simply normal sequential logic design. If this is difficult for you, you may want to go brush up on digital design techniques, before continuing.
 
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