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Configuring the Xilinx LogiCORE IP AXI IIC v1.02a

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dpaul

dpaul

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Hi,

I am using the Xilinx LogiCORE IP - AXI IIC v1.02a as a slave in my sub-system.

In the current situation I can READ and WRITE to the IIC data and configuration registers located in this slave device through AXI4-Lite transactions.

What I cannot achieve is getting some data and clock on the IIC side, transactions on SDA and SCL signals at the simulation level!

I am probably configuring the registers wrongly.

Can anyone pleased tell me the sequence necessary to program the config. and data registers so that I can get a data and clock out?
Any links where such sequence is mentioned would also help.
 

Basically no clock activity is being generated from the master transmitter.

The IIC clock is to be generated from the AXI clock (this I can view in my simulation) in the IP. I have set the parameters such that the the AXI clk is ~250 times the IIC clk.

Can anyone give me hints where to look for in this IP core, so that I can do some debug? What could be the reasons for the IIC clk not being generated?
 

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