beginner_EDA
Full Member level 4
Hi,
Is it possible to write bitstream (data width of lets say 4 bits i.e. std_logic_vector(3 downto 0))coming from some ports/pins of FPGA (lets say from some GPIO pins/Switch etc) into a file after some processing in FPGA using VHDL/Verilog?
I need it for test purpose.
Any help please.
Is it possible to write bitstream (data width of lets say 4 bits i.e. std_logic_vector(3 downto 0))coming from some ports/pins of FPGA (lets say from some GPIO pins/Switch etc) into a file after some processing in FPGA using VHDL/Verilog?
I need it for test purpose.
Any help please.