Fitter Failed--Quartus II- Version 12.0-- Total Memory Bits usage 0%, LE usage 1232%

Code VHDL - [expand]
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---ping pong buffer with interrupt from fpga for node 4 with data_ip
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity ping_pong_buffer is
  port(
       wr_clk_20mhz: in std_logic;
       clk_1mhz: in std_logic;
       rd_clk_50mhz: in std_logic;
       data_ip: in std_logic_vector(15 downto 0);
       addr: in std_logic_vector(5 downto 0);
       read_en : in std_logic;
       f_rst: in std_logic;
       int_full : out std_logic;
         led : out std_logic;
       data_op: out std_logic_vector(15 downto 0));
       
end entity ping_pong_buffer;
 
 
 
 
architecture behav_ping_pong of ping_pong_buffer is
  
---instantiate edge detector
component edge_detector_1mhz is
port
    (clk_1mhz: in std_logic;
     clk_20mhz: in std_logic;
     f_rst: in std_logic;
      detect: out std_logic); 
end component edge_detector_1mhz;
 
---state declaration
type name_of_my_states is (s0,s1,s2);
signal state:name_of_my_states;
 
signal count_led : std_logic_vector(23 downto 0) := (others => '0');
signal toggle : std_logic := '1';
---memory declaration
type mem_epi_1 is array(0 to 63) of std_logic_vector(15 downto 0);
type mem_epi_2 is array(0 to 63) of std_logic_vector(15 downto 0);
 
  signal Ram_a: mem_epi_1; 
  signal Ram_b: mem_epi_2;
 
  
  signal count_a : std_logic_vector(15 downto 0) := (others => '0');
  signal count_b : std_logic_vector(15 downto 0) := (others => '0');
  signal detect_1mhz: std_logic;
  signal count_capture : std_logic_vector(2 downto 0) := (others => '0');
  signal int_full_sig: std_logic:= '0';
  signal ram_a_ram_bn: std_logic:= '0';
  
begin
  detector: edge_detector_1mhz port map(detect => detect_1mhz, clk_1mhz => clk_1mhz, clk_20mhz => wr_clk_20mhz, f_rst => f_rst);
    
 
----logic to capture data at 250ns intervals and write into the ping pong buffer
 
WRITE_PROCESS : process(wr_clk_20mhz)
      begin
            if (f_rst = '0') then
              count_capture <= (others => '0');
              state <= s0;
                  count_led <= (others => '0');
              toggle <= '0';
            
            elsif(rising_edge(wr_clk_20mhz)) then
                if count_led = x"ffffff" then
                  toggle <= not toggle;
                  count_led <= (others => '0');
               else 
                  count_led <= count_led + '1';
            end if;
            
                if(int_full_sig = '1') then
                    ram_a_ram_bn <= not ram_a_ram_bn;
            end if;
              
    case state is
        
       when s0 =>   int_full_sig <= '0';
                    if(detect_1mhz = '1') then
                          state <= s1;
                        else
                          state <= s0;
                        end if;
 
           
       when s1 =>   int_full_sig <= '0';
                    if(count_capture = X"4") then
                      count_capture <= (others => '0');
                    else
                      count_capture <= count_capture + '1';
                    
                    if(count_capture = X"2") then
                      Ram_a(conv_integer(count_a)) <= count_a;
                    
                    if(count_a = X"3F") then
                          count_a <= (others => '0');
                          int_full_sig <= '1';
                          state <= s2;
                        else
                          count_a <= count_a + 1;
                          state <= s1;
                    end if;
                    end if;
                    end if;
                             
       when s2 =>   int_full_sig <= '0';
                    if(count_capture = X"4") then
                      count_capture <= (others => '0');
                    else
                      count_capture <= count_capture + '1';
                    
                    if(count_capture = X"2") then
                      Ram_b(conv_integer(count_b)) <= x"BC5A";
                    
                    if(count_b = X"3F") then
                          count_b <= (others => '0');
                          int_full_sig <= '1';
                          state <= s1;
                        else
                          count_b <= count_b + 1;
                          state <= s2;
                    end if;
                    end if;
                    end if;
                                 
                        
            end case;
            end if;
            end process;
            
            int_full <= int_full_sig;
             led <= '1';
            
READ_PROCESS: process(rd_clk_50mhz)
              begin
                if(rising_edge(rd_clk_50mhz)) then
                  if(read_en = '0') then
                    if(ram_a_ram_bn = '1') then
                  
                      data_op <= Ram_a(conv_integer(addr));
                    else
                      data_op <= Ram_b(conv_integer(addr));
              end if;
              end if;
              end if;
            end process;
            end behav_ping_pong;