abu9022
Member level 3
Hi friends
I have the Test Enable signal(TE) which should be write in VHDL,
clk is already written
Can I know how to write TE signal, below one is correct?
I have the Test Enable signal(TE) which should be write in VHDL,
Code:
clkperiod : integer := 4; -- system clock period
Code:
signal clk : std_logic := '0';
signal te : std_logic := '0';
constant ct : integer := clkperiod/2;
clk is already written
Can I know how to write TE signal, below one is correct?
Code:
clk <= not clk after ct * 1 ns;
te <= '0' after ct * 1 ns, '1' after ct * 1 ns, '0' after ct * 1 ns, '0' after ct * 1 ns;