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What can cause synthesis-dependent intermittents?

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Artlav

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Let's say i have a verilog design the size of a small SoC.
It is largely correct, and works nicely in an FPGA on one board.

On another identical board, however, it starts giving out intermittent errors, i.e. the I2C gets garbage sent out every 10 bytes.
But if i do some irrelevant change, like change HW version register value, to force a re-synthesis, then there is about a 50% chance that the design would work nicely in the second board as well.

Question is - what kind of errors or problems should i look for, given this kind of symptoms?
 

Sounds like a design without necessary timing constraints that is working by chance.

Or specific hardware problems like unstable design clock, insufficient supply bypassing, unstable voltage regulators, too much simultaneous switching noise, possibly PLLs losing lock, many possible problems, unfortunately.
 

Number one guess would be lack of constraints on a critical path. Synthesize it with seed A, and the P&R turns out to be okay. Then later you resynthesize it (which uses a different seed for place & route), and it violates timings.
 

Before starting with timing analysis I'd look at these things:

1. FPGA pin assignments - make sure all logic signals are assigned correctly to their corresponding hardware pins.

2. IPs - with simulation, make sure that the IPs in both cases work exactly the same way.

3. Input signals - make sure that all the input signals to the FPGA on your new board have the same value as in your old board. For example - external resets...

4. Signal & power integrity. Make sure your power isn't too noisy and that your signals look are proper.
 

FvM said:
Sounds like a design without necessary timing constraints that is working by chance.
Click to expand...
mrflibble said:
Number one guess would be lack of constraints on a critical path.
Click to expand...
Ah, nice.
There was indeed no constraint specified for I2C clock, and so far i haven't been able to reproduce the problem after adding it.

Thanks everyone for suggestions!
 

On any design you should always check the unconstrained path report, the first time you run it, and anytime you make changes to the constraints. This will help you to avoid situations like this where you have a missing constraint that results in intermittent failures.
 

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