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differences between for...loop and for...generate

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Binome

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Please tell me what difference there is between these 2 kinds of loop:
Code: 
init1 : process(clk,rst)
begin
	init_loop : for j in 0 to N-1 loop
	if rst='1' then	
		sigtmp_I(0,j) <= (others => '0');
		sigtmp_Q(0,j) <= (others => '0');
	elsif rising_edge(clk) then
		sigtmp_I(0,j) <= in_ifft_I(j);
		sigtmp_Q(0,j) <= in_ifft_Q(j);
	end if;
	end loop init_loop;
end process init1;

init2 : for j in 0 to N-1 generate
	if rst='1' then	
		sigtmp_I(0,j) <= (others => '0');
		sigtmp_Q(0,j) <= (others => '0');
	elsif rising_edge(clk) then
		sigtmp_I(0,j) <= in_ifft_I(j);
		sigtmp_Q(0,j) <= in_ifft_Q(j);
	end if;
end generate init2;
Thank you.
 

Only the first one (with the process) is legal VHDL syntax. You can't use sequential statements outside a process.

Do you own any VHDL text books?
 

A process is for runtime decisions: "what should we do if this signal goes high?"

A generate structure is for compile-time decisions: "what modules should be included in the design and how should they be connected?"
 

Ok, and what about a component written to be simulated then synthesized? Shoul I make the runtime or compile-time decisions easier?
 

If it's supposed to be both simulated and synthesized, then all the limitations for synthesis apply. For synthesis everything has to be determined compile-time.
 

A process is for runtime decisions: "what should we do if this signal goes high?"
Click to expand...
Nicely put,
But I think this statement tricked Binome into thinking that processes are meant for synthesizable logic only - which isn't true...processes can be used in simulation also...

Binome, think of "runtime" as everything that's "ticking" in your code and isn't associated with logic generation.
 

OK, I'll use for...generate in my component.
Thank you all.
 

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