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Is this a correct way to instantiate multiple modules

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anusha vasanta

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Code: 
genvar n;
	generate
	begin
	  Top_PipelinedCipher ROM1(clk,reset,data_valid_in,key_valid_in,key,mic_iv,valid_out,mic_iv_result);
	  assign mic_h1_out= (mic_iv_result^mic_h1);
	  Top_PipelinedCipher ROM2(clk,reset,data_valid_in,key_valid_in,key,mic_h1_out,valid_out,mic_h1_result);
	  assign mic_h2_out=(mic_h1_result^mic_h2);
	  Top_PipelinedCipher ROM3(clk,reset,data_valid_in,key_valid_in,key,mic_h2_out,valid_out,mic_h2_result);
	end
	endgenerate
 
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I don't understand the code. Why do you use generate at all, genvar isn't needed. It's just a list of regular module instantiations.
 
haa thankyou.without generate block we can do this right. i was just confused.
 

multiple iinstantiation problem in generate block

i was using the output of one istantiation module in generate block taking that output as input of another module this is a multiple instantion issue is this possible with verilog.

Code Verilog - [expand]
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Lgenvar m;
    generate
    for(m=BLOCKS;m<0;m=m-1)
    begin
      assign block_data[m]=data_new[(m*16)+15:(m*16)]; 
      assign block_out[m]=(mic_h2_result^block_data[m]);
      Top_PipelinedCipher ROM4(clk,reset,data_valid_in,key_valid_in,key,block_out[m],valid_out,block_result[m]);
      assign mic_h2_result=block_result[m];
    end
    endgenerate
 
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