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Pipeline Register Data Path

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forast

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I'm in need of a bit help regarding pipelining in verilog. I have a register module with enable and asynchronous reset and what I'm trying to do is create a structural model of the first stage. I have coded the register module already but I'm a little stumped on how to start the first part of this, I can show you what it asks and what I currently have. I prefer a little help so I can figure out what I gotta do. I'm just stuck and need something to jump start me.

Here's what I currently have:

Code: 
module register8bit (reset, clk, enable, d, q);

input reset;
input clk;
input enable;
input [7:0] d;
output [7:0] q;
reg [7:0] q;

always @ (posedge clk or posedge reset)
	if(reset)
		q = 0;
	else if (clk == 1)
		q = d;

endmodule

I'm trying to do the first stage of pipeline in this module, not sure if it's set up correctly but each A, B, C, and D has 8 bits input into each register then the 5th register is a mode. I'll then instantiate each of the register. Would this be correct?

Code: 
`include "register8bit.v"
module pipline (A, B, C, D, mode, clk, avg);

input [7:0] A; 
input [7:0] B; 
input [7:0] C; 
input [7:0] D;
input mode;
input clk;
output avg;

register8bit	reg1()

Question:

Code: 
Use five (5) register models to create the input registers (used as interface flip-flops to the rest of the circuit, Chap. 5) as shown. Four of the registers are to input the four 8-bit values A to D and only bit 0 of the fifth register is used to input mode. These registers form a 33-bit parallel-load register. (Alternatively, you may use a 33-bit register model).
 
Last edited:

There is an error in the register8bit module. The check for clk =1 is incorrect. The always block will be executed at the rising edge of clock as indicated by posedge clk. There is no need to check for clk=1.

- - - Updated - - -

I did not understand your 2nd question.
 

sharath666 said:
There is an error in the register8bit module. The check for clk =1 is incorrect. The always block will be executed at the rising edge of clock as indicated by posedge clk. There is no need to check for clk=1.

- - - Updated - - -

I did not understand your 2nd question.
Click to expand...

Basically I'm trying to use that register module to model after the pipeline data path. First stage combines X = A + B, second stage would be Y = A + C, third stage would be Z = Y + D. Using combinational logic of +/- and register module that is in the first one.
 

So X=A+B, Y=A+C and Z=Y+D is what you want to do...
You don't need to have a component called register8bit. You can define X,Y and Z as registers in the pipline module itself..
 

sharath666 said:
So X=A+B, Y=A+C and Z=Y+D is what you want to do...
You don't need to have a component called register8bit. You can define X,Y and Z as registers in the pipline module itself..
Click to expand...

Maybe I'm not quite understanding the concept of how to code it but from what I understand the interface register could be made into a 33 bit module, then the first stage could be 25 bit register, 2nd stage 17 bit register and the final stage an 8 bit register. In between each register there will be a combinational logic that either adds or subtracts the registers. So should I just model the 4 different modules (33 bit, 25 bit, 17 bit, and 8 bit) and have a combinational logic between each module that will either add or subtract the register?

Since the first stage has 4 different registers, each 8 bit and 1 register that is for mode. Second stage = 1 less register which equals 25 bits now, etc. This is what I'm grasping from the question but unsure if my logic is correct.
 

forast said:
Basically I'm trying to use that register module to model after the pipeline data path. First stage combines X = A + B, second stage would be Y = A + C, third stage would be Z = Y + D. Using combinational logic of +/- and register module that is in the first one.
Click to expand...
Did you actually mean:
X=A+B, Y=X+C, and Z=Y+D?

That seems more in line with the pipeline description you made where Z is the third stage.

Here is a diagram of what you want to do (an actual pipeline design), the code should be easy to generate based on the hardware design of the pipeline. I'm pretty sure you skipped doing this in the first place, hence your inability to "see" what the code should represent. You should never just start writing VHDL/Verilog code unless you understand what hardware you are describing. With a block diagram of the pipeline it's easy to write each individual register and the interconnect between them. After years of experience you can get away with just starting a design using a text editor, but that is because you will likely be writing the your code with some block diagram in mind from the start.

Capture.PNG

Pipelined in this fashion you can apply new values for A, B, C, D, and OP on every clock cycle. After a latency of 3 clocks you will get your first valid Z output and every clock after that will have valid Z's as long as there are valid inputs.
 
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