Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

polyphase filter-decimator on VHDL: some troubles

Status
Not open for further replies.
B

breezey

Newbie level 1
Joined
Nov 18, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
7
Hello to all! I have wrote the polyphase filter-decimator on VHDL, decimation factor M is 6.
The testbench showed decimation, but data in the out bus is not correct. Can someone look on my code and get an advice to me how i can fix troubles in it and what is it troubles? I have attached txt files with codes of the filter and his testbech.
 

Attachments

  • filter.txt
    13.4 KB · Views: 59
  • testbench.txt
    2.8 KB · Views: 38

Problems where it compiles but there is a problem in the code is really a problem for you to debug. If there is a problem like this - trace back the values through the sime. So from the output, look at the output drivers, followed by their drivers etc. Then check each stage to see if it is producing expected values.

as a side note - any reason you have used the non-standard std_logic_arith package rather than the standard numeric_std?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top