dpaul
Advanced Member level 5
Hi all,
I had used Xilinx CoreGen for block RAM generation, then have used the instantiation of it in my design. This RAM is working fine for read and writes - proven in RTL sim.
What I want now is to dump out this particular RAM's addresses and its contents correspondingly as this memory is accessed. This is want to do in the top-level test-bench. The RAM is instantiated somewhere deep down in the design hierarchy.
How can I do this, what are the steps to do this?
Any pointers...
Thanks,
dpaul
I had used Xilinx CoreGen for block RAM generation, then have used the instantiation of it in my design. This RAM is working fine for read and writes - proven in RTL sim.
What I want now is to dump out this particular RAM's addresses and its contents correspondingly as this memory is accessed. This is want to do in the top-level test-bench. The RAM is instantiated somewhere deep down in the design hierarchy.
How can I do this, what are the steps to do this?
Any pointers...
Thanks,
dpaul