Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Vivado and inline constraints in verilog.

Status
Not open for further replies.
mrflibble

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,720
Helped
679
Reputation
1,360
Reaction score
652
Trophy points
1,393
Activity points
19,551
Regarding constraints inside verilog code (as opposed to ucf/xdc files), how does Vivado handle that? In ISE it worked, but there were some sneaky gotcha's. Is Vivado better in this regard than ISE? Worse? About the same, including same sh!t as usual complete with gotcha's?

I mean the type of constraints where you for example specify an RLOC or BEL for a flip-flop.

Code Verilog - [expand]
1
2
3
4
5
6
7

(* RLOC=X0Y0 *) reg obligatory_flipflop;
(* RLOC=X1Y0 *) reg this_calls_for_another_flipflop;
 
always @(posedge clk) begin
    obligatory_flipflop <= ~obligatory_flipflop;
    this_calls_for_another_flipflop <= ~this_calls_for_another_flipflop;
end


And in ISE there were also types of constraints that would silently fail (raaaawr), so you would think they applied but nooooope. And then you specified the exact same constraint in an UCF entry and that would suddenly be totally acceptable, and give the expected result.

So I was wondering how this is in Vivado?
 

I haven't used location constraints, but I know that the following worked without problems:
Code: 
(* dont_touch = "true" *)
(* mark_debug = "true" *)
(* iob = "false" *)
(* shreg_extract = "no" *)
(* async_reg = "true" *)
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top