Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Low Power Design for Pseudo-Random number generator Using LFSR

Status
Not open for further replies.
A

abonic

Junior Member level 2
Joined
Dec 5, 2012
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,431
Hi Guys.
Recently, I'm getting interested in the PRN Generator Using Linear Feedback Shifting Register(LFSR).
If Low Power Performance is desired, which Logic Type and clock strategy are preferred.
 

This is no different to any other logic question. The power required will depend on the speed and logic family used. Faster clock speed will increase power consumption and CMOS is probably the most power efficient logic family to use but may not manage the speeds you require. You can even do it in software on a simple microcontroller if the speed and power suits your needs.

Brian.
 
  • Like
Reactions: abonic

    A

    abonic

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top