shaiko
Advanced Member level 5
Hello,
1.When multiplying 2 unsigned vectors in VHDL, must they be at the same length?
2.Is it legal to multiply an unsigned vector with an integer? Or both operands must be of the same type?
1.When multiplying 2 unsigned vectors in VHDL, must they be at the same length?
2.Is it legal to multiply an unsigned vector with an integer? Or both operands must be of the same type?