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Variable index in a for...generate loop

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Binome

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Hi,
here's a simplified piece of my code :
Code: 
loop1 : for i in 0 to log2N-1 generate
	variable n_b : integer := 0;
	variable n_p : integer := 0;

        loop2: for j in 0 to N/2-1 generate
		comp: component
		port map(
			clk => clk,
			rst => rst,
			en => en,
				
			p => sigtmp(j+n_p*2**(i+1)+n_b));
		
		if (n_b=2**(i+1)-1) then
			n_p := n_p+1;
			n_b := 0;
		else
			n_b := n_b+1;
		end if;
		
	end generate loop1;
end generate loop2;
Modelsim is telling "** Error: D:/*.vhd(128): (vcom-1450) Actual (indexed name) for formal "p" is not a static signal name.".
I understand the problem: indexes have to be constants but I can't find a solution to this problem.
Can someone help me?
 

The code is very simplified, and also contains errors.
I suggest posting the real code to get the real context.
 

I can't post everything because it's too long and because of privacy. Tell me were the errors are, I'll try to correct them first.
 

You will need to create an intermediate signal and then include that intermediate signal in the port map for 'p'. You can declare the new signal within the generate statement's scope like this...

Code: 
loop2: for j in 0 to N/2-1 generate
   signal sigtmp_slice:  ...
begin
   ...
end generate loop2;

You will then of course have to hook up the new intermediate signal sigtmp_slice to your existing sigtmp signal.
Kevin Jennings
 

Binome said:
I can't post everything because it's too long and because of privacy. Tell me were the errors are, I'll try to correct them first.
Click to expand...

1. You cannot declare variables inside a generate loop (they can only be declared inside a process/function/procedure
2. because of 1 - I dont understand how you can use them in a port map
3. if/else needs to be in a process/function etc.
 

OK,
here's a bigger part of my code:
Code: 
library ieee;
use     ieee.std_logic_1164.all;
use 	ieee.std_logic_arith.all;
use		ieee.math_real.all;

library work;
use		work.fft_pack.all;

entity fft_g is
	generic(
		Dwidth		: integer:=8;
		Twidth		: integer:=8;
		N			: integer:=128;
		log2N		: integer:=7;
		pipelined	: integer:=1;
		ifft		: boolean:=false);
	port(
		clk			: in  std_logic;
		rst			: in  std_logic;
		en			: in  std_logic;
		p_I			: in  fft_data(N-1 downto 0);
		p_Q			: in  fft_data(N-1 downto 0);
		x_I			: out fft_data(N-1 downto 0);
		x_Q			: out fft_data(N-1 downto 0);
		overflow	: out std_logic_vector(log2N-1 downto 0));
end fft_g;

architecture rtl of fft_g is

component butt is
	generic(
		Dwidth		: integer;
		Twidth		: integer;
		pipelined	: integer);
	port(
		clk			: in  std_logic;
		rst			: in  std_logic;
		en			: in  std_logic;
		twidd_cos	: in  std_logic_vector(Twidth-1 downto 0);
		twidd_sin	: in  std_logic_vector(Twidth-1 downto 0);
		p_I			: in  butt_data;
		p_Q			: in  butt_data;
		x_I			: out butt_data;
		x_Q			: out butt_data);
end component butt;

    type twiddtab is array(N-1 downto 0) of std_logic_vector(Twidth-1 downto 0);
	signal costab			: twiddtab;
	signal sintab			: twiddtab;
    
    signal sigtmp_I			: sig_tmp(log2N downto 0, N-1 downto 0);
    signal sigtmp_Q			: sig_tmp(log2N downto 0, N-1 downto 0);
    
    shared variable n_pack			: integer := 0;
    shared variable n_butt			: integer := 0;

begin
etages : for i in 0 to log2N-1 generate
	begin
		
    gentab :
		for idx in 0 to 2**i generate
			constant s : real := real(2**(Twidth-2))*sin(-real(idx)*real(2)*math_pi/real(2**i));
			constant sn : std_logic_vector(Twidth-1 downto 0) := conv_std_logic_vector(integer(s),Twidth);
			constant c : real := real(2**(Twidth-2))*cos(-real(idx)*real(2)*math_pi/real(2**i));
			constant cn : std_logic_vector(Twidth-1 downto 0) := conv_std_logic_vector(integer(c),Twidth);
		begin
			costab(idx) <= cn;
			sintab(idx) <= sn;
		end generate;

	papillons : for j in 0 to N/2-1 generate
	    signal sigtmp2_I			: sig_tmp(log2N downto 0, N-1 downto 0);
		signal sigtmp2_Q			: sig_tmp(log2N downto 0, N-1 downto 0);
	begin	
		twidd : butt
		generic map(
			Dwidth => Dwidth,
			Twidth => Twidth,
			pipelined => pipelined-1)
		port map(
			clk => clk,
			rst => rst,
			en => en,
				
			twidd_cos => costab(j),
			twidd_sin => sintab(j),
					
			p_I(0) => sigtmp2_I(i,j),
			p_I(1) => sigtmp2_I(i,j+N/2),
			p_Q(0) => sigtmp2_Q(i,j),
			p_Q(1) => sigtmp2_Q(i,j+N/2),
			x_I(0) => sigtmp2_I(i+1,j),
			x_I(1) => sigtmp2_I(i+1,j+N/2),
			x_Q(0) => sigtmp2_Q(i+1,j),
			x_Q(1) => sigtmp2_Q(i+1,j+N/2));
		
		sigtmp2_I(i,j) <= sigtmp_I(i,j),
		sigtmp2_I(i,j+N/2) <= sigtmp_I(i,j+n_pack*2**(i+1)+n_butt+2**i),
		sigtmp2_Q(i,j) <= sigtmp_Q(i,ind_p(i,j,n_pack,n_butt)),
		sigtmp2_Q(i,j+N/2) <= sigtmp_Q(i,j+n_pack*2**(i+1)+n_butt+2**i),
		sigtmp_I(i+1,j+n_pack*2**(i+1)+n_butt) <= sigtmp2_I(i+1,j),
		sigtmp_I(i+1,j+n_pack*2**(i+1)+n_butt+2**i) <= sigtmp2_I(i+1,j+N/2),
		sigtmp_Q(i+1,j+n_pack*2**(i+1)+n_butt) = sigtmp2_Q(i+1,j),
		sigtmp_Q(i+1,j+n_pack*2**(i+1)+n_butt+2**i) <= sigtmp2_Q(i+1,j+N/2));

		if (n_butt=2**(i+1)-1) then
			n_pack := n_pack+1;
			n_butt := 0;
		else
			n_butt := n_butt+1;
		end if;
		
	end generate papillons;
end generate etages;

end rtl;
Modelsim is complaining:
** Error: D:/*.vhd(99): Type error resolving infix expression "<=" as type ieee.std_logic_1164.STD_LOGIC_VECTOR.
 

Try putting ; instead of , on the end of your lines..
 

oh yeah, my bad.
I cant see the type declaration of sig_tmp - what is it?
 

Sorry, that's in a separate package file. It's:
type sig_tmp is array(natural range <>,natural range <>) of std_logic_vector(7 downto 0);
 

TrickyDicky said:
Try putting ; instead of , on the end of your lines..
Click to expand...
Binome said:
I thought , was needed instead of ; in a port map !
Click to expand...
TrickyDicky said:
oh yeah, my bad.
I cant see the type declaration of sig_tmp - what is it?
Click to expand...

Code VHDL - [expand]
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sigtmp2_I(i,j) <= sigtmp_I(i,j),
    sigtmp2_I(i,j+N/2) <= sigtmp_I(i,j+n_pack*2**(i+1)+n_butt+2**i),
    sigtmp2_Q(i,j) <= sigtmp_Q(i,ind_p(i,j,n_pack,n_butt)),
    sigtmp2_Q(i,j+N/2) <= sigtmp_Q(i,j+n_pack*2**(i+1)+n_butt+2**i),
    sigtmp_I(i+1,j+n_pack*2**(i+1)+n_butt) <= sigtmp2_I(i+1,j),
    sigtmp_I(i+1,j+n_pack*2**(i+1)+n_butt+2**i) <= sigtmp2_I(i+1,j+N/2),
    sigtmp_Q(i+1,j+n_pack*2**(i+1)+n_butt) = sigtmp2_Q(i+1,j),
    sigtmp_Q(i+1,j+n_pack*2**(i+1)+n_butt+2**i) <= sigtmp2_Q(i+1,j+N/2));

This is not right, you've got assignments with , at the end of the lines and a ); at the end of the last line that isn't matched. The code above this snippet doesn't have a matching ( either.

BTW, TABs s**k and mixing TABs with spaces is even worse. ;-)
 

Sorry for my absence. I couldn't use Modelsim for a moment.

Right ads-ee, I've corrected the , and ; for the assignments and other errors.
Now there's something I don't know how to do. It's the "if" I 'm trying to use as a concurrent instruction. I'm instantiating parts and each time I want to test a variable that's incremented sometimes. How can I do that?
 

Your questions doesnt make a lot of sense - please elaborate (maybe with code example)
 

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