Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Create a group of setup timing error

Status
Not open for further replies.

abu9022

Member level 3
Joined
Jan 2, 2013
Messages
60
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,715
1. How to create a group of setup timing error by reducing clock cycle time?

If I reduce clock cycle time it may be go slack negative, it's correct
 

Dear kind sir, please read the fine manual now in thread number 3. Are you going to keep making new threads along the lines of "how does trivial action regarding timing constraints work?" Read the"Xilinx timing constraints user guide", and all shall be clear. For link, see other thread. Or google title.

But yes, GENERALLY (so not your LEON thingy specifically) if you have a design with some amount of slack for a given clock, and THEN you reduce your clock period then your slack will also reduce and can go negative.
 

Yes, slack is negative for setup time volation.
Reducing clock cycle time reduce setup time window thus can cause setup time error.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top