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verilog for loop coding.i got error need endmodule due to for loop found

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vanabharathiram

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Code: 
module das (u,c,z);

    input    [0:31]u;
    input [0:31]c;
    output [0:31]z;
    genvar i;
    for (i=0;i<32;i=i+1)
    begin
        assign  c[i]=(u[i]&c[i]);
    end
endmodule

ERROR:HDLCompilers:26 - "dads.v" line 30 expecting 'endmodule', found 'for'

how to solve it
 
Last edited by a moderator:

Sequential statements like a for loop are valid only inside an always block or a function.

Review your Verilog text book or a tutorial.
 

One: see https://www.asic-world.com/verilog/verilog2k2.html on how to use a generate statement.

Two: assign c=(u&c); is going to be highly useless and not at all what you think it does. Because see three.

Three: What do you think the statement assign c=(u&c); is going to do? Or more properly, what kind of logic do you think the synthesizer will infer?

And four: what FvM said, best to review your verilog text book. Out of interest, which book are you using?

Well, and five: please use 
Code Verilog - [expand]
1

tags when posting verilog code. :)
 

Its missing generate .. endgenerate block

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module das (u,c,z);
 input [0:31]u;
 input [0:31]c;
 output [0:31]z;
 genvar i;
 generate 
 for (i=0;i<32;i=i+1)
 begin
   assign c[i]=(u[i]&c[i]);
 end
 endgenerate
 endmodule
 
Last edited by a moderator:

Verilog-2001 no longer requires generate/endgenerate - they are now optional. In addition to the problems mentioned by mrfibble, your error message reports it as being on line 30, yet you have only shown 11 lines of code. Many time when you get a missing end or endmodule, the problem is with the block of code that comes before the one the error is reported on.
 

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