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[SOLVED] compare two text files using verilog..........

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dipin

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hi

is there any way two compare two text files using verilog???

actually i need to compare expected output stored in a text file with the output of my program.is there any way to do this directly like c program.

did anyone have some documents or sample code..please help.
(this is for simulation purpose only)

thanks and regards
 

dipin said:
is there any way two compare two text files using verilog???
actually i need to compare expected output stored in a text file with the output of my program.is there any way to do this directly like c program.
Click to expand...
Use fileIO system tasks to read the "golden" file and compare word for word data from the UUT. This type of self checking testbench code is pretty easy to write and there are a lot of examples of using the fileIO system tasks to read in files on various websites.

The first four google hits:
http://www.asic-world.com/verilog/verilog2k3.html

This one is a comparison of pre-2001 fileio package with Verilog 2001. http://www.chris.spear.net/pli/fileio.htm
http://stackoverflow.com/questions/16630319/how-to-read-a-text-file-line-by-line-in-verilog
 
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    dipin

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man diff

I'd use some external script to do the comparison. No need to reinvent the wheel in a poorly implemented fashion in verilog.
 

Is there a reason you are trying to compare it in verilog? Why not tkdiff or any other utility commands?
 

Since you marked this as solved ... what solution did you end up using? Always useful to know for future people with the same problem.
 

Hi
mrflibble said:
Since you marked this as solved ... what solution did you end up using? Always useful to know for future people with the same problem.
Click to expand...

i have used $readmemb("input.txt",mem); to read the text file into a register and done the same to the other text file. then i compared the both registers . and finally used $fwrite to print the result into a another text file .
thanks for the help..
regards
 
Always interesting to hear what creative ways people use to do certain jobs. Thanks. :)
 
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    dipin

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Hi Dipin,

You did it in verilog for specific reason or you just wanted to explore it?
I always do the same in sw like Beyond compare, did you face any problem with that?

just asking for my future reference.
Thanks
 

hi verylsi,
verylsi said:
Hi Dipin,

You did it in verilog for specific reason or you just wanted to explore it?
I always do the same in sw like Beyond compare, did you face any problem with that?

just asking for my future reference.
Thanks
Click to expand...

actually i need to verify the output of a verilog program in which output writting into a text file. so i did this as a part of the testbench.
this comparison is a part of my program . so i done it in verilog itself

thanks and regards
 
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    verylsi

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