Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

driving clocking block signals in system verilog

Status
Not open for further replies.

vdeepakvlsi

Newbie level 1
Joined
Jul 27, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
6
why we use non-blocking assignment in driving clocking block signals?
 

[Moved]driving clocking block signals in System verilog

why we use non-blocking assignment for driving clocking block signals??
 
Last edited by a moderator:

See Section 14.16.1 Drives and nonblocking assignments of the 1800-2012 LRM.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top