Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Low Voltage Low Power gm/id design method.

Status
Not open for further replies.
S

skoda

Junior Member level 3
Joined
Aug 5, 2014
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
202
Hi,

I try to design symmetrics ota ( Sansen page 216 ), I use gm/id methodology ( i have learn it from D.M. Binkley tradeoffs), so a use this equation :

W/L= (1/IC) * (Idrain/Io) but when i need to design transistor Nmos for 25nA and IC=10, a will get W/L=1/256 which introduce me into problem with min. lenght which i have calculated by: Lmin= Wmin*L/W = 102.4u. Anyway cadence return me error because i have wrong Lmin or Lmax or Wmin Wmax.
(Io i mean technological current for 0.18um)

So is this methodology still propper for such low current? Please help to small student from Czech Republic :cry: .
 

Make series connection of few fets to get transistor with proper long L.
 
  • Like
Reactions: skoda

    S

    skoda

    Points: 2
    Helpful Answer Positive Rating
thank you dominik, and how can I do it ? I know that in property a can wrtie NM0<1:10> but i think this is parallel combination, and I dont want stack 8-10 transistor over full editor windows, there must be some trick for that, isn't it?
 

skoda said:
... I dont want stack 8-10 transistor over full editor windows, there must be some trick for that, isn't it?
Click to expand...

Make an extra cell from such a stack.
 
  • Like
Reactions: skoda

    S

    skoda

    Points: 2
    Helpful Answer Positive Rating
Using vector You are able to make serial connection, i.e. for instance M1<9:0> net from drain side should be labeled "net1,n<9:1>" while from source "n<8:0>,net2", where net1 is drain connection to other instance and net2 is source cennection to other instances (or supply/ground).
And rememeber to short all bulks of transistor together.
 
  • Like
Reactions: skoda

    S

    skoda

    Points: 2
    Helpful Answer Positive Rating
thank you guys! still i have problem with an extra cell ( I take a picutre of this extra cell). Anyway I need transistor with IC=10, Id=25nA NMOS, then I use Binkley equation W/L= (1/IC) * (Idrain/Io) and I get W/L=1/256, and if the Wmin=0.4u then the Lmin=102.4u. So I choose 8 transistor in seriies everyone gets AR=1/256 an L=13u (13*8=104u), but there is a problem that is same problem with lmin-lmax, so should I somehow devide AR=W/L=1/256 to this 8 transistor? 8serial.png
 

skoda said:
... L=13u (13*8=104u), but there is a problem that is same problem with lmin-lmax, so should I somehow devide AR=W/L=1/256 to this 8 transistor?
Click to expand...

If your sim-model allows (e.g.) Lmax=10µm, use a cell stack size of > 104/10 , i.e. 11 series transistors of L=104/11 .

Or use Dominik's method with one transistor array Mxy<11:1> and his suggested connection method by appropriate node naming.
 
  • Like
Reactions: skoda

    S

    skoda

    Points: 2
    Helpful Answer Positive Rating
Hi erikl,

I got your idea, but problem is that cadence still write error. In atteched picture,I tri to set W/L=1/128 because I need Id=50nA and IC=10, Lmin is 52um, so I do 3 series mosfet each L=20um. But cadence still see that each transistor has W/L=1/128 and L=20um and that is the point of problem, he judge it as single transistor and write Screenshot from 2014-08-11 21:02:18.pngScreenshot from 2014-08-11 21:02:32.pngerror. As you can see I try to make a Cellview but it doesnt help.
 

w=20um/128=156.25nm its probably too small value for your technology. Set the minimum width for your transistor (it should be around 250nm, but You should check in process manual) and set proper length.
 
  • Like
Reactions: skoda

    S

    skoda

    Points: 2
    Helpful Answer Positive Rating
skoda said:
... so I do 3 series mosfet each L=20um.
Click to expand...

If you have 3 MOSFETs with length=20µm in series (Ltot=60µm), you can use a width w=(1/128)*60µm = 0.47µm , which should be allowed in a 0.18µ process. This gives you a W/L = 1/128 .
 
  • Like
Reactions: skoda

    S

    skoda

    Points: 2
    Helpful Answer Positive Rating
Sorry guys Im just newbie and bad student :D I got the point and my problem is soved, thanks for your patience :)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top