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Analog circuits modeled using verilog and difficulties faced

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sun_ray

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Many times analog circuits are modeled in Verilog. What are the difficulties in modelling analog circuits by Verilog? How can it be overcome?
 

Many times analog circuits are modeled in Verilog.
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How? Verilog has no specific means to model analog circuits. Digital circuits with analog interface and the analog enviroment can be modelled in testbenches to a certain extent.
 

FvM said:
How? Verilog has no specific means to model analog circuits. Digital circuits with analog interface and the analog enviroment can be modelled in testbenches to a certain extent.
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What is the remedy then to cover up the deficiencies to model analog circuits with Verilog?

Regards
 

Verilog is not used to model analog circuits. Verilog-AMS extensions from Accellera do support analog and mixed signal.

https://en.wikipedia.org/wiki/Verilog-AMS
**broken link removed**

sun_ray, do you do any research on a subject before posting? It sure seems like you don't.
 

sun_ray said:
Many times analog circuits are modeled in Verilog. What are the difficulties in modelling analog circuits by Verilog? How can it be overcome?
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Now days most of the industries using verilog for modeling Analog in AMS circuits ...
it's not a RTL it's a BMOD only ..difficulty in the sense first the programmer need to understand the analog functionality and make a Black Box for this analog module (say one eg. for coding amplifier it should consider as comparator ..... ).
The need for coding analog block in verilog is to integrate the analog functionality with the SoC RTL before layout integration (these BMOD creation and integration is part of verification )
 

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