Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Urgent: Async. protocol to sync. protocol interface

Status
Not open for further replies.
N

normanmxw

Newbie level 2
Joined
Aug 18, 2004
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
21
Hi,

I seriously need some advice and reference materials on building an interface between an intel microprocessor (asynchronous protocol) to a synchronous SRAM (synchronous protocol).

Both the interface and SRAM are local on-chip components.

The challenge is that my interface is fixed at 60MHz local clock for synchronization. And without increasing the local clock rate, is there any alternatives to improving the throughput of my interface to the SRAM?

Any help is very much appreciated. Thank you.
 

Which protocol you are using and what is the clock rate of your Intel processor??
 

Hi,

it is a microcontroller intel 8051..... the signals are:data bus, address bus, control signals (Chip Select, Read, Write)... there is no clock connected to my chip. Which is why I need to specially interface it to my synchronous SRAM, my chips's clock is 60MHz max.
 

Here are my suggestions:

1. Sample & detect the falling edge of ALE and latch P0 & P2 for the address upper and lower address.

2. Detect the fallowing of P3[6] and P3[7] for read & write operation with the address latched during ALE being asserted. You should have so much time to do I/O with this slow MCU.

If you need some more info. I can help you ;^)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top