Looking for materials about DDR IO interface

DDR IO design.

Hi, all.
for ddr controller design, I can get blenty material , but I could not find any materail about the DDR interface IO. you know, for correctly latching DQ, the
timing relationship between DQ and DQS is very important.
Special circuit for conquer temprature and voltage, etc is needed.
Can anyone give some source or proposal for designing DDR interface in ASIC.


Thanks very much.

Re: DDR IO design.

I think you can find some clues on Xilinx app notes.

DDR IO design.

http://www.xilinx.com/bvdocs/appnotes/xapp200.pdf

**broken link removed**

**broken link removed**

Re: DDR IO design.

hi
DDR IO design has some challenges like
1. it needs special analog cell
2. Timing critical
3. Board problems
4. too many patents


1:: read side is more critical than write side. You will have narrow Data window to deal with. So, you need some analog cells which can compensate the process, temperature variations. First you need to choose whether you want to do source synchronous or synchronous design on read side. If it is source synchronous, you need to use DQS to latch the data. If you want to do it in a synchronous way, you need to use the clock to latch the data.

2:: You need to do rough timing calculation (budgetting) before you start with design. Timing analysis need to be very exhaustive.

3:: Different people wants to terminate on board in a different way. One of the most popular way is terminate to VREF. That means, when it is inactive, we don't know whether it is 1 or 0.

4:: Lots of guys who started using DDR rams patented their design ideas. The people who started late, doesn't have lot of options.

Check micron and samsung websites, they have some good appnotes.

tx
sri